Fedevel — Advanced PCB Layout with Altium Designer

I attended Robert Feranec's Advanced PCB Layout training and studied high-speed PCB placement, stackup, impedance, signal integrity, length matching and manufacturing outputs in Altium Designer.

I attended Advanced PCB Layout training delivered by motherboard design engineer Robert Feranec. Working in Altium Designer, the course examined how placement, stackup, impedance, return paths, crosstalk and length matching interact in high-speed board design.

Topics I covered in the course:

https://academy.fedevel.com/courses/online-advanced-pcb-layout-course

Placement: positioning the CPU, memories, power supplies, connectors, protection components and related circuitry

Basic Rules and Basic Stackup: initial design rules and stackup settings

CPU Fanout: placement and fanout in high-density areas

DDR3 Preliminary Layout: layer use, pin swapping and bank swapping

Board Fanout: fanout techniques, good practices and recommendations

Planning the Layout: high-speed interfaces, wide buses and power distribution

Crosstalk: calculation and minimization

Impedance and Stackup: impedance calculation and stackup decisions

High-Speed Design Rules and Routing: recommendations and examples

Layer Ordering

Selecting the Number of Layers

Layout: routing peripherals, buses and power

Length Matching: DDR2/3, PCIe, HDMI, LVDS and Gigabit Ethernet

Memory Routing: T-branch and fly-by topologies, calibration and related considerations

Polygons and Power Planes: working practices and useful rules

PCB Checking: recommendations for design review

Length Tuning: differential-pair tuning and completion of memory routing

Finishing the PCB: manufacturing notes, mechanical drawing layers and supporting information

Generating and Checking Gerber Files

What I Took from the Course

One of the most useful aspects of the training was seeing high-speed PCB constraints as coupled physical decisions rather than independent checklist items. Adding serpentine routing simply to reach a target length can affect coupling and impedance, while connecting a high-speed bus between two endpoints is incomplete without considering its reference plane and return-current path.

DDR, PCIe, HDMI, LVDS and Gigabit Ethernet have different timing and topology requirements, so a single generic routing rule is not sufficient for every interface. A design review therefore has to consider the physical consequences of placement and routing in addition to schematic correctness.

This training strengthened the electronics background I use when reading the hardware layer beneath embedded and mechatronic software. Related context: What Is Mechatronics?.