Computer Organization and Basic Processor Structure

This article is the expanded version of the computer-organization notes I kept during the 2013-2015 course period. I preserve the original sequence from register transfers and microoperations to the basic-computer model. In later revisions I compared those concepts with modern processor terminology and corrected ambiguities. The educational basic-computer model is deliberately kept separate from the internal organization of a contemporary x86, Arm or RISC-V core.

Unit 1: Fundamentals of Digital Logic Circuits

Digital computer

A digital computer represents and processes information through discrete states. Binary representation is dominant because two-state electronic circuits are robust, composable and naturally mapped to Boolean algebra.

At the logical level a computer can be viewed as a composition of:

• combinational circuits that compute functions of current inputs,
• sequential circuits that preserve state,
• memory structures,
• datapaths that transport and transform data,
• control logic that determines which operations occur and when.

Computer architecture and organization

Architecture describes properties visible to software, such as the instruction set, register model, addressing behavior and architectural memory semantics.

Organization describes how those architectural requirements are implemented: buses, control signals, ALU structure, internal registers, cache hierarchy, pipeline organization and other microarchitectural choices.

Two processors may implement the same ISA with very different internal organizations.

Logic gates and truth tables

AND, OR and NOT provide the basic Boolean operations. NAND and NOR are universal; XOR represents inequality/parity-like behavior. A truth table lists the output for every input combination and therefore gives a complete finite description of a combinational Boolean function.

Boolean algebra and De Morgan's laws

Boolean identities allow logical expressions to be transformed without changing their truth function. De Morgan's laws are especially important:

(A B)' = A' + B'
(A + B)' = A' B'

They explain transformations between AND/OR structures and NAND/NOR implementations.

Karnaugh maps

Karnaugh maps arrange minterms in Gray-code order so adjacent cells differ in one variable. Grouping adjacent ones for SOP, or zeros for POS, eliminates changing variables and reduces an expression. The method is practical for small variable counts; larger synthesis problems are handled algorithmically.

Combinational circuits

A combinational circuit has no stored logical state: outputs are functions of current inputs. Examples include adders, multiplexers, decoders, encoders, comparators and ALUs.

Half and full adders

A half adder computes:

S = A XOR B
C = A B

A full adder includes a carry input:

S    = A XOR B XOR Cin
Cout = AB + ACin + BCin

Cascading full adders creates a ripple-carry adder. Its simplicity comes with carry-propagation delay.

Flip-flops and sequential logic

Sequential circuits combine combinational logic with state. Flip-flops sample and retain state under clock/control conditions. D, T, JK and SR models emphasize different next-state relationships.

A latch is generally level-sensitive, whereas an edge-triggered flip-flop changes state around a clock edge. Setup and hold requirements arise from the physical storage element; violating them can cause metastability.

Unit 2: Digital Components

Integrated circuits and logic families

An integrated circuit contains many active/passive components on a substrate. Digital logic families define electrical characteristics such as logic thresholds, drive capability, propagation delay and power. TTL and CMOS are historically important families; modern processors use highly integrated CMOS implementations rather than board-level textbook gates.

Decoders and encoders

A decoder maps an n-bit code to one of up to 2^n output selections. It can implement minterms, memory address selection and control decoding.

An encoder maps active input lines to a compact code. Priority encoders define which input wins when several are asserted.

Multiplexers

A multiplexer selects one data input according to control bits. It can implement both data routing and Boolean functions. Internal processor datapaths frequently use mux-like selection structures even when the physical implementation is optimized beyond a literal gate schematic.

Registers

A register stores a multi-bit word. Registers may support:

• parallel load,
• clear/reset,
• hold,
• shift,
• increment/decrement,
• selected transfer to a bus.

Shift registers

A shift register moves bits left or right on clock events. Serial/parallel conversion, delay and simple sequence generation are typical uses. A bidirectional shift register can select left or right movement; a universal register can additionally support parallel load and hold.

Counters

A binary counter advances through a state sequence. Ripple counters propagate transitions between stages and accumulate delay. Synchronous counters clock all state elements together and compute the next state combinationally.

Main memory

Main memory provides addressable storage for instructions and data. From the processor's view, an access identifies an address and transfers a word/byte through a defined interface. Physical DRAM timing is more involved than the simple read/write model presented in basic organization.

RAM and ROM

RAM permits ordinary read/write operation. SRAM retains bits in bistable cells while powered and does not require refresh; DRAM stores charge and requires refresh.

ROM-like storage represents persistent or programmed contents. Modern firmware may reside in flash or other nonvolatile technology rather than literal mask ROM.

Unit 3: Data Representation

Number systems

Binary is the native positional representation for digital circuits. Octal and hexadecimal provide compact human-readable grouping of three and four bits respectively.

Fractional binary conversion uses negative powers of two. Not every decimal fraction has a finite binary representation, which is one source of floating-point approximation.

Character encodings

ASCII historically maps character symbols to numeric codes. Modern software often uses Unicode encodings, but the organizational principle is the same: characters become bit patterns through a defined code.

BCD

Binary-coded decimal stores each decimal digit separately in binary. It is not the same as representing the full decimal number as a binary integer. BCD is useful when decimal digit identity is operationally important.

Complements and signed values

Two's complement is the dominant signed-integer representation. For n bits its range is:

-2^(n-1) ... 2^(n-1)-1

Negation is formed by complementing bits and adding one, except that the most-negative number has no positive counterpart in the same width.

Overflow

Carry out is an unsigned arithmetic concept. Signed overflow occurs when the mathematical signed result is not representable in the destination width. For two's-complement addition, adding two operands of the same sign and obtaining the opposite sign indicates overflow.

Fixed and floating point

Fixed-point formats assign an implicit scaling to an integer bit pattern. They provide predictable resolution and are useful in embedded/DSP systems when dynamic range is bounded.

Floating-point formats represent sign, exponent and significand. IEEE 754 defines widely used binary formats and special values such as infinities and NaNs. Floating-point arithmetic is finite-precision arithmetic; associativity and exact decimal behavior cannot be assumed in general.

Parity and error control

A parity bit detects any odd number of flipped bits but cannot correct errors and misses even-numbered error patterns. Stronger error-detecting/correcting codes add structured redundancy and exploit distance between valid codewords.

Unit 4: Register Transfers and Microoperations

Internal structure of a digital computer

At an educational register-transfer level, a processor can be described as registers connected by buses and functional units. Control signals select sources, destinations and operations each clock step.

Register transfer language

Register-transfer notation expresses microoperations such as:

R2 <- R1

meaning that the contents of R1 are transferred into R2 when the corresponding control condition is active.

A conditional transfer may be written conceptually as:

P: R2 <- R1

where P is the control function.

Microoperation

A microoperation is an elementary operation on information stored in registers. Major classes are:

• register transfer,
• arithmetic,
• logic,
• shift.

An architectural instruction normally requires multiple such internal operations.

Buses

A common bus lets several registers share transfer wiring. Only one source may drive a shared single-source bus at a time, while one or more destinations may load from it according to control.

A multiplexer-based bus selects one register as source. A tri-state implementation historically allowed multiple devices to connect electrically to a shared bus provided only one driver was enabled. Modern on-chip structures are often synthesized as mux/interconnect networks rather than literal internal tri-state wiring.

Memory read and write

A simplified read sequence is:

AR <- address
DR <- M[AR]

A simplified write is:

AR <- address
M[AR] <- DR

Real memory hierarchies include cache, queues and coherence, but the register-transfer form is useful for understanding command/data flow.

Arithmetic microoperations

Arithmetic microoperations include addition, subtraction, increment, decrement and related transformations. Subtraction can reuse an adder through two's complement:

A - B = A + B' + 1

An arithmetic circuit often combines operand selection with a parallel adder and carry input.

Logic microoperations

Bitwise AND, OR, XOR and complement operate independently on corresponding bit positions. They are used for masking, setting, clearing and toggling bit fields.

A mask can preserve selected bits:

R <- R AND mask

or set selected bits:

R <- R OR mask

Shift microoperations

Logical shifts insert zeros. Arithmetic right shift preserves the sign interpretation for two's-complement values by replicating the sign bit under the usual model. Rotations wrap shifted-out bits around to the other end.

ALU and shifter

An ALU selects arithmetic or logic functions according to a control word. Adding a shifter enables compound datapath operations. In a real processor, execution units may be specialized and deeply pipelined, but the ALU-plus-shifter model remains useful for basic datapath reasoning.

Unit 5: Basic Computer Structure and Instruction Execution

Educational basic computer

The classic basic-computer model is intentionally small. It provides a visible relationship among memory, registers, instruction fields, timing signals and microoperations. It should be treated as a teaching architecture, not as a literal model of a modern superscalar CPU.

Instruction format

A simple instruction can contain:

operation field + address field + addressing-mode bit

The operation determines what to do; the address/mode determines how to obtain the operand or control target.

Core registers

Typical registers in the educational model include:

• PC: program counter,
• IR: instruction register,
• AR: address register,
• DR: data register,
• AC: accumulator,
• temporary and input/output registers.

The program counter identifies the next instruction location. The instruction register holds the current instruction. An accumulator architecture uses AC as a primary arithmetic operand/result register.

Direct and indirect addressing

Direct addressing uses the instruction's address field as the effective memory address. Indirect addressing treats that field as the location of another address:

direct:   EA = address field
indirect: EA = M[address field]

This illustrates a general distinction between a value encoded in an instruction and a value obtained through another level of memory reference.

Fetch cycle

A simplified fetch is:

AR <- PC
IR <- M[AR]
PC <- PC + 1

After fetch, control decodes the opcode and addressing mode, obtains any required effective address, executes the operation and proceeds to the next instruction or interrupt sequence.

Memory-reference instructions

The teaching instruction set commonly includes operations such as:

• AND: bitwise AND memory operand with accumulator,
• ADD: add memory operand,
• LDA: load accumulator,
• STA: store accumulator,
• BUN: unconditional branch,
• BSA: branch-and-save-return-address style subroutine support,
• ISZ: increment memory word and skip if zero.

Their value is not the mnemonic set itself but that each can be decomposed into a precise sequence of register transfers.

Register-reference and I/O instructions

Register-reference instructions operate directly on processor state, for example clear/complement/shift accumulator or control execution. I/O instructions exchange data/status with simple input/output registers and flags in the educational model.

Instruction cycle

The complete instruction cycle combines:

fetch
  ↓
decode
  ↓
indirect/effective-address phase if required
  ↓
execute
  ↓
interrupt check/service if required

Timing and hardwired control

A hardwired control unit derives control signals from decoded instruction bits, timing states and status conditions. It can be fast but becomes complex as the instruction set and control interactions grow.

Interrupts

An interrupt transfers control to a service routine in response to an event. Correct handling requires saving enough architectural state to resume the interrupted computation according to the architecture's rules. Interrupt latency, masking, priority and nesting are system-level design issues beyond the minimal teaching sequence.

Unit 6: Assembly Programming on the Basic Computer

Machine and assembly language

Machine language encodes operations and operands as bits. Assembly language gives symbolic names to opcodes, addresses and constants. An assembler translates symbolic source into machine representation.

A typical assembly line contains a label, operation and operand/directive fields. Labels create symbolic addresses whose numeric values are resolved by the assembler.

Pseudo-operations

Assembler directives do not necessarily correspond to processor instructions. They can reserve storage, define constants, set an origin or terminate source processing.

Two-pass assembly

A classic two-pass assembler works as follows:

1. first pass: determine addresses and build the symbol table,
2. second pass: translate instructions using resolved symbol values.

Forward references explain why a second pass is useful.

Symbol table and diagnostics

The symbol table maps names to attributes such as addresses. An assembler should diagnose duplicate symbols, undefined symbols, illegal mnemonics and out-of-range operands rather than silently emit incorrect code.

Loops, multiplication and division

A minimal instruction set may not include hardware multiply/divide instructions. Repeated addition/subtraction or shift-and-add algorithms demonstrate how more complex arithmetic can be constructed from simpler operations.

Shift-and-add multiplication examines multiplier bits and conditionally accumulates shifted multiplicands. The same conceptual decomposition underlies hardware multipliers even when optimized implementations use more advanced structures.

Subroutines and stack considerations

A subroutine needs a return address and a convention for arguments, temporary values and preserved state. The basic computer's BSA-style mechanism illustrates one simple approach.

Nested and recursive calls require return addresses to be stored independently, which naturally motivates a stack. A general calling convention further defines which registers are caller/callee saved, how parameters are passed and how stack frames are organized.

I/O programming

Programmed I/O repeatedly checks device state and transfers data under CPU control. Interrupt-driven I/O lets other work proceed until service is required. DMA transfers blocks between device and memory with less per-word CPU involvement.

Unit 7: Microprogrammed Control

Role of the control unit

The control unit sequences datapath actions required by instructions. In microprogrammed control, those low-level control steps are represented by microinstructions stored in a control memory.

Control memory and control address register

A control memory contains microinstructions. The control address register selects the current microinstruction. Sequencing logic determines the next control address from sequential flow, branches, opcode mapping and condition tests.

Microinstruction format

A microinstruction can directly encode control signals or encode fields that are further decoded. The design tradeoff is similar to instruction encoding:

• wide horizontal formats expose more parallel control bits,
• vertical formats encode operations more compactly but need additional decoding.

Microprogram sequencing

A microsequencer must support:

• next-address increment,
• conditional branches,
• mapping from instruction opcode to microprogram entry point,
• microprogram subroutines where used.

Mapping and fetch microprogram

Opcode mapping selects the starting microaddress of the corresponding instruction routine. A common fetch routine is shared, then control branches to an execution routine and eventually returns to fetch.

Indirect-address handling can likewise be a shared microprogram routine.

Hardwired versus microprogrammed control

Hardwired control realizes the sequencing directly with logic. Microprogrammed control stores control sequencing as microcode. The historical distinction is useful, but modern processors may combine decoded micro-operations, ROM/patchable microcode and extensive hardwired scheduling/control. The textbook categories are conceptual endpoints rather than mutually exclusive modern implementations.

Unit 8: Central Processing Unit

CPU organization

A CPU organization can use an accumulator, stack, general-purpose registers, or a hybrid. General-purpose register organization reduces memory traffic and permits instructions to name several working values.

Register file and control word

A register file provides multiple registers with read/write selection. A control word can specify source registers, destination register, ALU function and shift behavior. This is a register-transfer description of a datapath control interface.

Stack organization

A stack follows last-in-first-out order. PUSH places an item on the stack and updates the stack pointer; POP removes an item. Stacks support expression evaluation, temporary storage and procedure calls.

Postfix notation is convenient for stack machines because operators follow operands:

A B + C *

can be evaluated by pushing operands and applying operators to stack-top values.

Instruction formats

Instruction formats can be classified by explicit operand count:

• three-address,
• two-address,
• one-address,
• zero-address.

A three-address instruction may encode separate destination and two sources. Two-address forms reuse one operand as destination. Accumulator machines often use one explicit address. Stack machines can use zero-address arithmetic instructions because operands are implicit on the stack.

Addressing modes

Common modes include:

• implied,
• immediate,
• direct,
• indirect,
• register,
• register indirect,
• auto-increment/decrement,
• indexed,
• base plus displacement,
• PC-relative.

The effective-address equation makes each mode clearer than memorizing names. For example:

base/displacement: EA = Rbase + displacement
indexed:           EA = base + Rindex
PC-relative:       EA = PC + signed displacement

The exact naming and encoding differ among ISAs.

Program-control instructions and status flags

Branches, calls, returns and traps modify the normal sequential PC flow. Status flags can record zero, sign, carry, overflow and other condition information according to the ISA.

RISC and CISC

Traditional RISC design emphasizes simple regular instruction formats, load/store operation, many registers and pipeline-friendly decoding. Traditional CISC design permits richer memory operations and more complex encoding.

The distinction is not absolute in contemporary processors. Modern x86 implementations decode complex instructions into internal micro-operations, while Arm and RISC-V families include sophisticated vector, atomic and cryptographic extensions. ISA style and microarchitecture must be considered separately.

Unit 9: From Basic Organization to Modern Microarchitecture

Mapping the basic model forward

The teaching datapath still provides useful concepts:

PC -> instruction fetch
registers -> architectural/physical register state
ALU -> execution units
control -> decode, scheduling and retirement logic
memory -> cache hierarchy + main memory

but a modern core performs many operations concurrently and speculatively.

Pipelining

Pipelining overlaps stages of several instructions. A simple conceptual pipeline can be:

fetch -> decode -> execute -> memory -> write-back

Throughput can approach one completed instruction per cycle in an ideal single-issue model after filling, while the latency of one instruction still spans multiple stages.

Hazards

A structural hazard occurs when operations compete for one resource. A data hazard occurs when one instruction depends on another's result. A control hazard arises when the next instruction address depends on a branch or other control transfer.

Forwarding and stalls address some data hazards. Branch prediction/speculation reduces control-hazard cost. Replicated or pipelined resources reduce structural conflicts.

Out-of-order execution

Out-of-order cores allow independent instructions to execute when their operands and functional units are ready rather than waiting strictly for earlier unrelated instructions. To preserve the architectural model, results are generally retired/committed in an order that maintains precise state semantics.

Register renaming

Register renaming maps architectural register names to a larger set of physical registers. This removes false name dependencies such as write-after-write and write-after-read relationships while preserving true data dependencies.

Cache hierarchy and virtual memory

Caches exploit temporal and spatial locality to bridge CPU and main-memory latency. Multiple levels trade capacity, latency and bandwidth.

Virtual memory translates process virtual addresses to physical memory, provides protection/isolation and permits mappings that need not correspond directly to contiguous physical storage. A TLB caches recent address translations.

ISA versus microarchitecture

The central distinction is:

ISA: what software is promised
microarchitecture: how a processor implements that promise

An ISA specifies the architectural state transitions visible to software. Pipelining, issue width, cache organization, speculative execution and physical-register structures are implementation decisions unless the architecture explicitly exposes relevant behavior.

Overall Framework

The course can be followed as one hierarchy:

Boolean logic
   ↓
combinational and sequential components
   ↓
registers and buses
   ↓
microoperations
   ↓
datapath + control
   ↓
instruction cycle
   ↓
assembly-level software
   ↓
CPU organization
   ↓
modern microarchitecture

The value of the basic model is not that modern processors literally look like it. Its value is that it makes every instruction understandable as controlled state transitions over storage and functional units. Modern processors add concurrency, speculation, caching and physical indirection, but they still have to preserve the architectural behavior promised to software.