TLB

TLB — A processor cache that stores recent virtual-to-physical address translations to avoid repeated page-table walks.

Computer-Architecture Context

A translation lookaside buffer caches recent virtual-to-physical address translations so the processor can avoid a page-table walk on most memory references. Large pages and good address locality can reduce miss rate, while context or address-space changes may require invalidation or refilling depending on the architecture.

Conceptual Boundary

A TLB is not a cache of application data. Its entries describe address translations and related permissions or attributes used by virtual-memory hardware.

Related Architecture Concepts

• Virtual Memory
• Page Fault
• CPU Cache
• Huge Page