Cache Coherence
Cache Coherence — Hardware protocol machinery that coordinates cached copies of the same memory location across multiple cores or processors.
The Hardware Problem
Several cores can hold cached copies of the same memory line. When one core modifies that data, other cores must not continue using an obsolete copy. Cache-coherence protocols coordinate ownership, sharing and invalidation to maintain a coherent view.
MESI-like protocols track states such as modified, exclusive, shared and invalid. Write-heavy shared data can force ownership to move repeatedly between cores, increasing coherence traffic and latency.
False Sharing
Two threads may update logically independent variables that happen to occupy the same cache line. The resulting unnecessary invalidations are known as False Sharing.
Coherence Is Not the Language Memory Model
Cache coherence concerns physical cached copies. A processor or language memory-consistency model defines which ordering of loads and stores can be observed by other execution contexts. The layers interact, but they are not the same concept.