Cache Line
The fixed-size block of data transferred between main memory and a CPU cache, rather than an individual variable.
Even when a variable occupies only a few bytes, a processor normally fetches the cache line that contains it. This helps contiguous access patterns, but independent fields written by different cores can create False Sharing when they share the same line.
Cache lines are why data-layout decisions cannot be reduced to total memory consumption. Alignment, access pattern, and coherence traffic can change the behaviour of otherwise identical code across processors.