CPU Cache
A hierarchy of small, fast memories near the processor that reduces effective memory latency by retaining recently or predictably reused data.
CPU caches exploit temporal and spatial locality to reduce effective memory-access latency. Modern processors usually provide several levels such as L1 and L2 plus a last-level cache whose sharing topology depends on the architecture. Cache-line placement, false sharing, and coherence traffic can materially affect concurrent software.
Hit ratio alone does not explain performance. The level at which a miss is satisfied, memory bandwidth, prefetch behavior, and working-set layout all matter. For latency-sensitive systems, hardware counters and tail latency should be evaluated alongside average execution time.
Related: Cache Line, False Sharing, TLB, CPU Affinity, Computer Architecture.