Electronics I and II: Analog and Digital Circuit Fundamentals

The material is organized around the physical relationships that determine circuit behavior rather than around memorized formulas. The sequence runs from Ohm's and Kirchhoff's laws through semiconductor devices, transistor biasing, amplifiers, and the transition to digital electronics. Sign conventions, operating regions, and ideal-model assumptions are kept explicit because mixing these levels is a common source of error in elementary circuit analysis.

Unit 1: Fundamental Electrical Quantities and Circuit Elements

Field-line views make charge, potential, and voltage relations physically interpretable from the start.

1.1. Electric Charge

Electric charge is a basic physical quantity measured in coulombs. The elementary charge magnitude is approximately:

e = 1.602 x 10^-19 C

Current in conductors can be understood as the rate of charge transfer, while electrostatic behavior depends on the distribution of charge and the resulting field.

1.2. Electric Field

Electric field is force per unit positive test charge:

E = F / q

It is a vector. In circuit theory the field is usually not solved directly; lumped voltage and current variables provide a simpler model when physical dimensions and signal frequencies justify the lumped-element approximation.

1.3. Potential Difference

Voltage is energy per unit charge:

V = W / q

A voltage is always a difference between two points. A circuit chooses a reference node so other node voltages can be expressed relative to it.

1.4. Electric Current

Current is the time rate of charge flow:

i(t) = dq/dt

Conventional current direction is defined as positive-charge flow. Electron drift in metals is opposite to conventional current.

1.5. Energy and Power

Electrical power is:

p(t) = v(t) i(t)

Under the passive sign convention, positive power means the element absorbs energy and negative power means it delivers energy.

For constant values:

W = P t

connects power and transferred energy.

1.6. Resistance and Ohm's Law

For an ideal linear resistor:

v = i R

and therefore:

P = VI = I^2 R = V^2 / R

where the equivalent forms follow from Ohm's law.

1.7. Ohmic and non-ohmic Elements

An ohmic element has an approximately linear v-i relation over the operating range being considered. Semiconductor junctions, lamps over large temperature ranges and many other devices are nonlinear; a constant resistance is not a complete model for them.

1.8. Temperature Dependence

For a limited temperature interval, resistance is often approximated as:

R(T) = R0 [1 + alpha (T - T0)]

The coefficient depends on material and the approximation range. Semiconductor temperature behavior can be very different from a metal resistor's positive coefficient.

1.9. Inductor

An ideal inductor relates voltage to current change:

v(t) = L di/dt

and stores magnetic-field energy:

W = 1/2 L i^2

Ideal inductor current cannot change discontinuously without infinite voltage. Real inductors add winding resistance, parasitic capacitance, core loss and saturation limits.

1.10. Capacitor

An ideal capacitor follows:

i(t) = C dv/dt

and stores electric-field energy:

W = 1/2 C v^2

Ideal capacitor voltage cannot change discontinuously without infinite current. Real capacitors have ESR, leakage, dielectric loss and voltage/frequency limits.

1.11. Ideal Sources

An ideal voltage source maintains its specified voltage regardless of current; an ideal current source maintains its specified current regardless of voltage. These are analysis models. Real sources have finite voltage/current compliance and internal impedance.

1.12. Reading the Electronics Chain Through Circuits, Measurement, and the analog-digital Boundary

The course sequence forms two connected layers:

charge, voltage, current
        ↓
R, L, C and circuit laws
        ↓
AC response and filters
        ↓
semiconductor physics
        ↓
diodes and transistors
        ↓
amplifiers and op-amps
        ↓
logic levels and Boolean algebra
        ↓
combinational/sequential digital circuits

Analog and digital electronics are not independent worlds. Logic gates are transistor circuits; timing and noise margins are analog properties; digital arithmetic is built from Boolean structures implemented in physical devices. The abstraction boundary is useful precisely because each lower layer supplies predictable behavior to the layer above it.

Unit 2: DC Circuits and Circuit Analysis

To solve a DC circuit, choose a reference node and identify unknown node voltages. Form node or supernode equations according to the placement of ideal voltage sources, maintaining consistent current directions. After solving, check Ohm's law in each branch, current balance at nodes, and total power balance. A mathematically obtained answer that violates power conservation commonly indicates a sign or connectivity error.

2.1. Electromotive Force

A source converts non-electrical energy into electrical potential difference. The historical term electromotive force is measured in volts even though it is not a mechanical force.

2.2. Maximum Power Transfer

For a Thevenin source with resistance Rth, a purely resistive load receives maximum power when:

RL = Rth

The theorem concerns maximum delivered load power, not maximum efficiency. At the matching point in the simple DC-resistive model, source resistance dissipates the same power as the load.

2.3. Series and Parallel Resistors

Series resistors carry the same current:

Req = R1 + R2 + ...

Parallel resistors share the same voltage:

1/Req = 1/R1 + 1/R2 + ...

For two resistors:

Req = R1 R2 / (R1 + R2)

2.4. Kirchhoff's Current Law

KCL follows charge conservation. At a node, the algebraic sum of branch currents is zero:

sum i_k = 0

A consistent sign convention is enough; currents assumed in the wrong physical direction simply solve to negative values.

2.5. Kirchhoff's Voltage Law

KVL states that the algebraic sum of voltages around a closed lumped circuit path is zero:

sum v_k = 0

This is consistent with energy conservation under the assumptions of ordinary lumped circuit theory.

2.6. Nodal Analysis

Nodal analysis chooses a reference node, assigns unknown node voltages and applies KCL. Branch currents are written in terms of voltage differences and element relations.

For a resistor between nodes a and b:

i_ab = (Va - Vb) / R

The resulting simultaneous equations determine node voltages.

2.7. Mesh Analysis

Mesh-current analysis assigns loop currents to independent meshes in a planar circuit and applies KVL. Shared elements contain the algebraic difference of adjacent mesh currents.

Nodal analysis is often more direct for circuits with many current sources; mesh analysis can be convenient for voltage-source-dominated planar circuits.

2.8. Voltage Divider

For two series resistors:

Vout = Vin R2 / (R1 + R2)

provided the output is unloaded or the load has already been incorporated into the equivalent resistance. Connecting a load changes the divider ratio.

2.9. Current Divider

For two parallel resistors carrying total current I:

I1 = I R2 / (R1 + R2)
I2 = I R1 / (R1 + R2)

The lower-resistance branch carries more current.

2.10. Thevenin Equivalent

A linear two-terminal network can be represented at its port as an ideal voltage source Vth in series with Rth or, for AC linear networks, impedance Zth.

Vth is the open-circuit terminal voltage. The equivalent resistance can be found by suppressing independent sources and looking into the port, or with test-source methods when dependent sources are present.

2.11. Norton Equivalent

The same linear network can be represented by a current source In in parallel with Rn:

Rn = Rth
In = Vth / Rth

for the ordinary non-degenerate resistive case.

2.12. Source Transformation

A voltage source V in series with R is equivalent at its terminals to a current source I = V/R in parallel with the same resistance. The equivalence concerns terminal behavior, not internal element currents in the original network.

2.13. Tolerance, Loading, and Measurement Uncertainty

Nominal schematic values are not exact physical values. Resistor tolerance, capacitor voltage and temperature dependence, amplifier offsets, ADC reference error, and supply variation should be considered together. A robust design works across credible worst cases, not only at the typical point.

Measurement equipment also becomes part of the circuit. Probe capacitance can disturb a fast node, while meter input resistance can load a high-impedance divider.

Tolerance analysis, Monte Carlo simulation, and corner testing are useful before production, but only to the extent that the model captures relevant parasitics. Differences between simulation and bench measurements are often evidence about missing physical effects.

2.14. Verifying Circuit Results by Measurement

Circuit calculations use nominal values, while physical circuits include component tolerance, temperature, supply variation, and instrument loading. Simulation output, bench measurement, and datasheet limits are therefore different forms of evidence.

A measurement record should state probe type, bandwidth, grounding, sample rate, and supply conditions. Probe capacitance or instrument input resistance can materially change high-impedance or high-frequency nodes.

Design decisions should consider credible corner cases rather than one typical value. Datasheet min/typ/max limits, tolerance analysis, and bench measurements together define the conditions under which a circuit can be expected to operate.

Checking a node solution against loading and power balance. An ideal 12 V source feeds a series 2 kΩ resistor and a 4 kΩ resistor from the node to ground. The node voltage is V = 12·4/(2+4) = 8 V. Series current is I = (12−8)/2000 = 2 mA, matching the only outgoing branch current, 8/4000 = 2 mA. Source power is 12·0.002 = 24 mW; resistor dissipation is (0.002)²·2000 = 8 mW and (0.002)²·4000 = 16 mW, satisfying power balance. If an 8 kΩ measurement load is connected across the lower resistor, its equivalent becomes 4 kΩ ∥ 8 kΩ = 8/3 kΩ, dropping the node voltage to approximately 6.86 V. The earlier value changes because the unloaded assumption no longer holds, not because Kirchhoff's laws fail. Measurement input impedance therefore belongs in the circuit model.

Unit 3: AC Circuits, Phasors and Frequency Behavior

Frequency behavior is not only a circuit topic; visible light itself is an electromagnetic wave with spectral structure.

For sinusoidal steady-state analysis, first determine whether the sources share the same angular frequency. Convert quantities at a common frequency into phasors using a consistent RMS or peak convention, solve the impedance network, and return to the time domain if necessary. Distinct frequency components must not be combined into one phasor network. Power calculations must preserve both the voltage-current phase difference and the stated amplitude convention.

3.1. Sinusoidal Signals

A sinusoid can be written:

v(t) = Vm sin(omega t + phi)

with amplitude Vm, angular frequency omega = 2 pi f, frequency f, and phase phi.

3.2. RMS Value

For a sine wave:

Vrms = Vm / sqrt(2)
Irms = Im / sqrt(2)

RMS gives the DC-equivalent heating effect in a resistor.

3.3. Phasors

For linear steady-state sinusoidal analysis, a sinusoid can be represented by a complex phasor. Differentiation becomes multiplication by j omega and integration division by j omega, converting differential equations into algebraic impedance relations.

3.4. Resistor, Inductor and Capacitor in AC

Ideal resistor:

Z_R = R

Voltage and current are in phase.

Ideal inductor:

Z_L = j omega L

Current lags voltage by 90 degrees in the ideal sinusoidal steady-state model.

Ideal capacitor:

Z_C = 1 / (j omega C)

Current leads voltage by 90 degrees.

3.5. Series RLC

For series RLC:

Z = R + j(omega L - 1/(omega C))

At series resonance:

omega0 = 1 / sqrt(LC)

the reactive terms cancel ideally and impedance is resistive.

3.6. AC Power

Using RMS phasors, complex power is:

S = V I* = P + jQ

where P is real power, Q reactive power and |S| apparent power. Power factor is cos(phi) for sinusoidal single-frequency conditions.

3.7. RC Filters

A first-order RC low-pass with output across the capacitor has:

H(jw) = 1 / (1 + jwRC)

and cutoff:

fc = 1 / (2 pi RC)

A first-order high-pass with output across the resistor has:

H(jw) = jwRC / (1 + jwRC)

Under appropriate frequency/time-scale assumptions, RC networks can approximate differentiation or integration, but those approximations are valid only over a limited band.

3.8. Faraday Cage and Electrostatic Shielding

A Faraday cage exploits the redistribution of charge on a conductive boundary to modify electrical coupling between interior and exterior regions. In electrostatic equilibrium the electric field inside the bulk of an ideal conductor vanishes. This must be distinguished from the field inside an empty cavity: if a charge or other internal source is present, the cavity field need not be zero everywhere. Shielding from an external electrostatic source and the surface-charge distribution induced by an internal source are distinct boundary-value problems.

Free charges move over the conductor until equilibrium is established and the surface becomes equipotential. A real enclosure nevertheless has finite conductivity, contact resistance, and geometric discontinuities. Grounding can set a reference potential and serve protective purposes, but grounding is not a universal prerequisite for the basic electrostatic shielding effect. Source placement and enclosure geometry matter alongside material conductivity.

Gauss's law and ideal-conductor boundary conditions express the electrostatic limit:

∮ E · dA = Q_enclosed / ε₀
E_conductor = 0              (electrostatic equilibrium)
E_tangential = 0             (ideal conductor surface)

These are static-field relations, not evidence that a cage perfectly rejects every time-varying electromagnetic field. Radio-frequency shielding additionally requires modeling induced currents and wave interaction with the enclosure. Circuit Theory treats coupling and reference potentials; Measurement Systems addresses experimental verification.

3.9. Frequency and Material Dependence of Electromagnetic Shielding

For time-varying excitation, shielding depends on electric- and magnetic-field components, the near-field or far-field character of the source, and conductivity (σ), permeability (μ), and dielectric properties. Under a planar far-field approximation, reflection, absorption, and internal multiple reflections can be considered; however, those contributions cannot be combined as universally independent scalar terms for every geometry. Near-field source impedance differs from that of a plane wave, while highly conductive materials alone may provide limited low-frequency magnetic shielding.

For a good conductor within an appropriate approximation, skin depth is estimated by:

δ ≈ √(2 / (ω μ σ))
ω = 2πf

Skin depth is the characteristic distance over which field amplitude falls approximately to 1/e in the conductor, not the overall shielding effectiveness of an enclosure. A wall several skin depths thick can still leak through joints, doors, ventilation slots, and cable penetrations. Higher frequency can increase attenuation through the metal while simultaneously making geometrical apertures electrically larger and potentially more problematic.

Shielding effectiveness must identify the quantity being compared:

SE_E = 20 log₁₀(|E_reference| / |E_shielded|) dB
SE_H = 20 log₁₀(|H_reference| / |H_shielded|) dB
SE_P = 10 log₁₀(P_reference / P_shielded) dB

These metrics need not coincide when wave impedances differ. Measurement point, source type, polarization, distance, and bandwidth must be stated before any decibel figure can be generalized. The underlying theory is developed in chapters 1–4 of Celozzi, Araneo, and Lovat's Electromagnetic Shielding.

Unit 4: Physical Foundations of Semiconductors

4.1. Energy Bands

In solids, allowed electron energies form bands separated by forbidden regions. Electrical behavior depends strongly on band occupancy and band-gap size.

Conductors have readily available states for charge transport; insulators have large effective barriers; semiconductors have a moderate band gap that allows carrier concentration to be controlled by temperature, light and doping.

4.2. Electrons and Holes

A missing electron in the valence-band bonding structure can be modeled as a positively charged mobile hole. Semiconductor current can therefore be described through electron and hole carriers.

4.3. Intrinsic Semiconductor

A pure semiconductor has thermally generated electron-hole pairs. At equilibrium in an ideal intrinsic material, electron and hole concentrations are equal.

4.4. Doping

Adding donor impurities produces n-type material with electrons as majority carriers. Acceptor impurities produce p-type material with holes as majority carriers. The material remains electrically neutral on the macroscopic scale.

4.5. Fermi Level

The Fermi level is an energy reference connected to carrier occupancy probability. Doping shifts its position relative to intrinsic material and the band edges. It should not be interpreted simply as a physical voltage source inside the semiconductor.

4.6. Temperature and Light

Semiconductor conductivity generally changes strongly with carrier concentration and mobility. Temperature can increase intrinsic carrier generation, while illumination can generate additional electron-hole pairs. A photoresistor exploits conductivity change with light, though its material/device physics differs from a PN photodiode.

Unit 5: PN Junctions and Diodes

5.1. PN Junction

When p-type and n-type regions form a junction, carrier diffusion leaves ionized dopants near the interface, creating a depletion region and built-in electric field. At equilibrium, diffusion and drift balance and net current is zero.

5.2. Forward and Reverse Bias

Forward bias reduces the effective barrier and allows significant carrier injection. Reverse bias increases the depletion field and only a small leakage current flows until breakdown mechanisms become important.

5.3. Diode Equation

An idealized junction relation is:

I = Is [exp(Vd/(n Vt)) - 1]

where Is is saturation current, Vt thermal voltage and n an ideality factor. Real devices add series resistance, leakage, recombination, capacitance and thermal effects.

5.4. Circuit Models

Useful models include:

• ideal diode,
• constant-voltage-drop approximation,
• piecewise-linear model,
• exponential model.

The appropriate model depends on the required accuracy and operating region.

5.5. Load Line

A diode/transistor circuit can be solved graphically by intersecting the nonlinear device characteristic with the external circuit's load line. The intersection is the operating point.

5.6. Rectifiers

A half-wave rectifier passes one half-cycle. A full-wave rectifier uses both half-cycles, commonly through a bridge or center-tapped topology.

A reservoir capacitor reduces output ripple by charging near waveform peaks and supplying the load between peaks. Ripple depends on load current, capacitance and line/rectified frequency; the capacitor does not produce perfectly constant DC.

5.7. Zener Diode and Breakdown

A reverse-biased junction can enter breakdown. Zener tunneling dominates at lower breakdown voltages and avalanche multiplication at higher ones, with a transition region where both contribute. A Zener diode is designed to operate safely in breakdown with current limiting.

5.8. Tunnel Diode and LED

A tunnel diode uses heavy doping and quantum tunneling, producing a negative-differential-resistance region. An LED emits photons when electron-hole recombination releases energy in a suitable direct-band-gap semiconductor. LED current must be limited by the driving circuit.

Unit 6: BJT Transistors

6.1. Structure and Currents

A BJT consists of emitter, base and collector regions in NPN or PNP form. Terminal currents satisfy:

IE = IC + IB

In the forward-active region a common approximate relation is:

IC ≈ beta IB

but beta varies with device, current, temperature and operating point and should not be treated as an exact circuit constant.

6.2. Operating Regions

• cutoff: both junction conditions correspond to essentially off operation,
• forward active: used for amplification,
• saturation: both relevant junctions are forward biased and the transistor behaves as a strongly conducting switch rather than a linear current amplifier.

6.3. Common-base, common-emitter and common-collector

Common-emitter provides substantial voltage/current gain and phase inversion. Common-collector, or emitter follower, provides voltage near unity gain with useful impedance transformation. Common-base offers low input impedance and can be useful at high frequency.

6.4. Biasing

Bias establishes a quiescent point so the signal can vary without immediately clipping or leaving the intended operating region. Voltage-divider bias with emitter degeneration provides better stability than a simple fixed base-current bias because emitter feedback reduces sensitivity to transistor gain.

6.5. DC Load Line and Q Point

The external collector circuit imposes a relation such as:

VCE = VCC - IC RC

for the simplest common-emitter stage. The intersection with the transistor behavior determines the quiescent operating point Q.

Unit 7: FET and MOSFET

7.1. Field-effect Transistor

A field-effect transistor controls channel current primarily through an electric field. It has high input impedance because the controlling gate ideally draws little steady-state current.

7.2. JFET

A JFET uses a reverse-biased gate junction to control channel width. In the usual n-channel model, increasingly negative VGS reduces drain current. The transfer characteristic is often approximated by Shockley's relation within the appropriate region:

ID = IDSS (1 - VGS/VP)^2

with device-specific sign conventions.

7.3. Transconductance

Small-signal transconductance is:

gm = dID/dVGS

at the operating point. It links a small gate-voltage change to drain-current change.

7.4. MOSFET

A MOSFET uses an insulated gate. Enhancement n-channel MOSFETs require gate-to-source voltage beyond threshold to form a strong inversion channel.

Basic regions are commonly described as:

• cutoff,
• triode/linear,
• saturation.

The word saturation does not mean the same device physics as BJT saturation. In a MOSFET, saturation is the region commonly used for analog current-source/amplifier operation, while the low-resistance linear region is used for an on-switch.

Small-signal gain in a common-source MOSFET amplifier depends on its DC bias point. In a simplified saturation-region small-signal model with output resistances neglected, voltage gain is related approximately to −g_m·R_D. A sufficiently large input can move the operating point into cutoff or the triode region, invalidating that linear approximation. Calculated gain must therefore be checked against input amplitude, output swing, supply limits, and loading. The amplifier use of the saturation region should not be confused with the fully enhanced switching condition of a power MOSFET.

7.5. Bias Point, small-signal Model, and Operating Region

An amplifier must first establish a valid DC operating point. Small-signal analysis then linearizes the device around that point. Mixing the two views leads to incorrect gain and headroom estimates.

For a BJT, cutoff, forward-active, and saturation regions correspond to different junction biases. For a MOSFET, cutoff, triode, and saturation describe different relations among gate, drain, source, and threshold voltages.

The small-signal parameters are operating-point dependent. Gain therefore changes when bias current, load, temperature, or device parameters change.

7.6. Operational-amplifier Nonidealities

The ideal op-amp model is useful, but real circuits are constrained by finite open-loop gain, gain-bandwidth product, slew rate, input offset, bias current, output-current limit, common-mode range, and output swing.

Negative feedback can control closed-loop gain only while the amplifier remains inside these limits. A mathematically valid resistor ratio can still produce saturation, slew-rate distortion, or instability in hardware.

Unit 8: Small-Signal Amplifiers and Operational Amplifiers

Changing magnetic flux is the physical basis of induction-driven sensing and measurement elements.

8.1. Amplifier Concept

An amplifier uses energy from a supply to produce an output signal related to an input signal with controlled gain. Voltage, current, transconductance and power gain are different quantities.

8.2. Small-signal Model

A nonlinear transistor can be linearized around a bias point for sufficiently small variations. The resulting incremental model allows AC gain and impedance to be analyzed with linear circuits while the DC bias is handled separately.

8.3. Common-emitter and common-base Stages

A common-emitter BJT stage typically provides inverted voltage gain. Emitter resistance can stabilize gain and improve linearity at the cost of gain. Bypass capacitors can make the feedback frequency-dependent.

A common-base stage has low input impedance and no common-emitter phase inversion; its high-frequency behavior can be useful in some topologies.

8.4. Feedback

Negative feedback trades open-loop gain for controlled closed-loop gain, improved linearity, wider useful bandwidth and reduced sensitivity to parameter variation, provided the loop remains stable. Positive feedback is used deliberately in oscillators and hysteretic comparators but can destabilize an amplifier.

8.5. Operational Amplifier

An ideal op-amp model assumes:

• infinite open-loop gain,
• infinite input impedance,
• zero output impedance,
• infinite bandwidth.

Real op-amps violate all of these assumptions. The ideal rules are valid only when the circuit is operating with negative feedback and the required output remains within input common-mode, output swing, slew-rate, current and stability limits.

8.6. Inverting Amplifier

For the ideal negative-feedback model:

Vo / Vi = -Rf / Rin

The inverting input is a virtual reference relative to the non-inverting input, not an actual short circuit.

8.7. Non-inverting Amplifier

Vo / Vi = 1 + Rf/Rg

for the standard ideal topology.

8.8. Voltage Follower

A follower ties output to the inverting input and drives the non-inverting input from the source. Ideal gain is one, with high input and low output impedance.

8.9. Summing and Difference Amplifiers

Multiple input resistors at the inverting node create a weighted summer. A difference amplifier subtracts scaled input voltages when resistor ratios are matched appropriately.

8.10. Common-Mode Rejection in Differential Inputs

A component varying identically at both inputs is common-mode; the voltage difference is differential. A real difference amplifier can be modeled as v_o = A_d(v₂−v₁) + A_c v_cm, with v_cm = (v₁+v₂)/2. Common-mode rejection ratio is CMRR = 20 log₁₀|A_d/A_c|. It is finite and often depends on frequency, signal level, and circuit layout. Although an ideal operational amplifier draws no input current, practical rejection depends on resistor tolerances, source impedance imbalance, and the valid input common-mode range.

When resistor ratios in a difference amplifier are mismatched, identical input signals do not cancel completely. A test first applies an identical sinusoid to both inputs to measure common-mode output, then equal opposed signals to estimate differential gain. The tests are repeated across frequency and within safe operating ranges; clipping or excess common-mode voltage invalidates a linear CMRR calculation. Twisting conductors may improve symmetry of electromagnetic coupling, but interference rejection also requires suitable differential sensing and impedance balance. The measured noise floor of a complete instrument cannot be replaced by one nominal CMRR value from an amplifier specification.

8.11. Differentiator and Integrator

Ideal op-amp differentiator:

Vo = -RC dVi/dt

Ideal integrator:

Vo = -(1/RC) integral Vi dt

Practical circuits limit low/high-frequency gain to control noise, offsets and stability.

8.12. Separating the Operating Point from Small-Signal Behaviour

Two different tasks are often mixed together in analog-electronics problems: finding the DC operating point and analysing small variations around that point. In a BJT or MOSFET amplifier, bias conditions come first. Whether the device is in cutoff, an active region, or saturation determines whether a later small-signal model is valid. A small-signal equivalent is not an alternative circuit that can replace the nonlinear device under every condition; it is a local linearization around an established operating point.

Operational-amplifier analysis has a similar boundary. The relation v+ ≈ v- is not a universal property that can be imposed on every op-amp circuit. It is a powerful consequence used when negative feedback is present, the output remains within the supply limits, and the device operates in its linear region. Once the output saturates or the feedback sign changes, carrying the same assumption forward produces an invalid solution.

For a diode, the piecewise-linear model, constant-voltage-drop model, and exponential model offer different balances between simplicity and accuracy. The appropriate model depends on the question. A first approximation of a rectifier may need only a constant drop, whereas temperature dependence, incremental resistance, or a precise current calculation requires a richer model.

The first question in an electronics solution is therefore often not “which formula should I use?” but “which operating region is the device in, and is my model valid there?” If the computed result violates the assumed region, the algebra may be correct while the circuit solution is not.

8.13. Bandwidth and Stability Limits of Operational Amplifiers

The ideal operational amplifier assumes infinite open-loop gain, zero input current, and unlimited bandwidth. Real amplifiers exhibit frequency-dependent open-loop gain, while the feedback network sets closed-loop gain and stability. The gain–bandwidth product under a dominant single-pole approximation is a useful first estimate, but it is not sufficient for multi-pole devices, capacitive loads, or operation near rail limits.

Large signals are subject to the slew-rate limit, which is distinct from small-signal bandwidth. A sinusoid requires a maximum slope of \(2\pi f V_{pk}\), suggesting the necessary condition \(SR\geq 2\pi f V_{pk}\) for undistorted tracking. At 10 kHz and 2 V peak, the required slope is approximately 0.126 V/µs. This condition does not establish correct operation unless input/output ranges, common-mode limits, output current, and thermal constraints are also satisfied.

Stability analysis examines the phase behavior of loop gain: additional high-frequency poles or capacitive loading may reduce phase margin. A low-amplitude square-wave experiment can expose overshoot, ringing, and settling characteristics. Probe capacitance can itself alter the observed response, so measurement connections are part of the experimental setup.

8.14. Signal Integrity and Coupling in Shielded Circuits

An enclosure can reduce electric-field interference at high-impedance analog inputs, but capacitive, inductive, and common-impedance coupling represent different physical paths. A metal box does not automatically repair poor PCB return paths, inadequate local decoupling, or the loop formed by a measurement probe. Shielding and filtering are complementary rather than interchangeable techniques.

A first-order capacitive coupling model and the induction relation are:

i_interference ≈ C_parasitic · d(v_source − v_victim)/dt
v_induced = −dΦ_B/dt

The dominant coupling path cannot be identified without considering source-current loop area, frequency content, victim impedance, and cable return paths. An enclosed ADC and a shielded cable require different termination decisions. There is no context-free rule requiring every shield to be connected at exactly one end or both ends; frequency, protective safety, and equipotential conditions all matter.

Unit 9: Analog and Digital Systems

An analog system represents information over a continuous range. A digital system represents information with discrete symbols/levels. Physical digital circuits are still analog electrical systems underneath; noise margins and timing allow continuous voltages to be interpreted reliably as discrete logic values.

Digital representation supports reproducible storage, logical processing, error detection and programmable behavior, but it introduces sampling, quantization, finite word length and interface requirements when interacting with analog signals.

9.1. ADC and DAC as the analog-digital Boundary

An analog-to-digital converter samples a continuous-time signal and maps amplitude to a finite code. Resolution alone does not define accuracy. Offset, gain error, differential/integral nonlinearity, aperture uncertainty, reference noise, and front-end noise also affect the result.

For an ideal N-bit converter with full-scale range V_FS, one LSB is approximately V_FS / 2^N.

Effective number of bits (ENOB) summarizes noise and distortion performance and is usually lower than the nominal resolution.

Sampling also requires an anti-aliasing decision. Frequencies above the usable Nyquist band can fold into the measured spectrum if the analog front end does not suppress them.

A DAC performs the reverse boundary transformation but still has finite settling time, monotonicity, glitch energy, reference error, and output-drive constraints.

9.2. From the Measurement Chain to Learning Systems

A learning model does not observe the physical world directly. It observes numerical samples produced by sensors and the analog front end. The strongest connection between electronics and AI therefore comes from the measurement chain that defines what the model can see, not from the generic statement that AI can be used in electronic systems.

A practical sensing path commonly follows this order:

physical quantity
↓
sensor / transducer
↓
amplification and analog filtering
↓
sampling and ADC
↓
digital signal
↓
feature or learned representation
↓
model

Information lost in the first half cannot always be recovered by choosing a larger model. Saturation clips information. Insufficient bandwidth suppresses fast changes. Poor grounding or electromagnetic interference raises the noise floor. An inadequate sampling rate creates aliasing. Limited ADC resolution can map distinct small variations to the same code. The model does not know the physical cause; it only learns the distribution presented to it.

In vibration, audio, or biosignal classification, for example, a field change in analog gain may become distribution shift if training data were acquired under a different gain. Sensor replacement, thermal drift, or supply noise can similarly alter the numerical distribution for the same physical event. Model accuracy and measurement accuracy can no longer be evaluated independently.

Signal-to-noise ratio is therefore not only an electronics metric. When useful signal energy disappears into noise, discriminative information is reduced. Analog filtering is also not made obsolete by downstream digital processing or machine learning; anti-alias filtering establishes the physical bandwidth before sampling.

The digital side creates another connection. Quantized models may perform inference with narrow integer arithmetic. Fixed-point representation, saturation, registers, counters, and data paths become direct constraints in resource-limited edge systems. The objective is not to imitate a general-purpose processor, but to realize the required dataflow with sufficient numerical quality and bounded energy.

The boundary must remain explicit. Electronics does not teach loss functions, generalization, or learning optimization. It teaches the physical reliability of the measurement that feeds those methods. A learning system inherits the limits of its sensor and acquisition chain; no statistical method can reconstruct information that was never captured.

9.3. Measurement Noise and Robust Summaries

Robust statistics asks how much an estimator degrades under small departures from an idealized model. For electronic measurement series, the median and MAD suppress gross deviations, while the influence function characterizes the local effect of one corrupted observation and the breakdown point indicates how long an estimator remains useful as sensor saturation or impulsive noise becomes more prevalent. In heavy-tailed or contaminated data, decisions based only on the mean and standard deviation can be misleading.

• Show how one outlier can shift the mean in sensor or laboratory measurements.
• Compare median/MAD summaries with mean/standard-deviation summaries.
• Separate component-tolerance distributions from actual fault observations.

Unit 10: Number Systems and Codes

Positional binary, octal and hexadecimal representations follow the same radix-weight principle discussed earlier. MSB denotes the most significant bit and LSB the least significant bit in a numerical word; physical transmission order is a separate interface convention.

Binary fractions use negative powers of two. BCD stores decimal digits independently. Weighted BCD codes assign explicit bit weights; Excess-3 is obtained by adding three to each decimal digit before four-bit encoding.

Gray code arranges consecutive codewords so only one bit changes. It is useful in position encoders and clock-domain pointer schemes because intermediate multi-bit transition ambiguity can be reduced, though correct synchronization still matters.

Parity adds simple redundancy. Octal/hexadecimal are compact notations rather than new machine encodings. Alphanumeric codes map characters to numeric values.

Unit 11: Boolean Algebra and Karnaugh Maps

Boolean variables take logical values. AND, OR and NOT form the basic operations; truth tables provide exhaustive finite behavior.

Identities, absorption and De Morgan's laws support simplification. SOP represents a function as a sum/OR of product terms; POS represents a product/AND of sum terms. Minterms correspond to truth-table 1 rows and maxterms to 0 rows in canonical forms.

Karnaugh maps use Gray adjacency to combine minterms/maxterms and eliminate variables. Don't-care states may join groups only when either output value is acceptable for those input combinations.

Unit 12: Logic Gates and Logic Families

AND, OR, NOT, NAND, NOR, XOR, XNOR and buffers are logical functions implemented by electronic circuits. Diode logic can implement limited functions but lacks inversion/gain. DTL and TTL are historically important bipolar logic families. CMOS became dominant for highly integrated digital systems because of its static-power and scaling characteristics, though dynamic switching power and leakage remain major design concerns.

Fan-in is the number of inputs a gate accepts; fan-out describes how many compatible inputs an output can drive under specified electrical constraints. Propagation delay is the time between a relevant input transition and the corresponding output transition.

Unit 13: Combinational Logic Circuits

Combinational design maps present inputs to present outputs. Analysis moves from circuit to expression/truth table; synthesis moves from behavior to simplified logic and then to gates.

NAND/NOR universal implementation follows Boolean transformation. Multiplexers route selected data and can synthesize functions. Encoders compress one-of-many signals; priority encoders resolve simultaneous requests. Decoders expand an input code to selected outputs and are used in address/control selection.

Unit 14: Arithmetic Logic Circuits

A one-bit comparator determines <, =, > for two bits; multi-bit comparison prioritizes the highest-order unequal bit.

Half/full adders implement binary addition. A ripple-carry adder cascades carries and therefore has width-dependent propagation delay.

A half subtractor handles two input bits; a full subtractor adds borrow-in. In practical arithmetic units, subtraction is commonly implemented by an adder using two's complement rather than by an entirely separate datapath.

Binary multiplication forms shifted partial products. Array multipliers arrange these products as a regular two-dimensional network; faster multipliers use recoding and reduction trees to shorten the carry-propagation path.

Unit 15: Sequential Circuits and Counters

A sequential circuit's outputs and next state depend on stored state as well as current inputs. An SR latch provides basic bistable storage; NAND and NOR versions use opposite active-level conventions.

A latch is level-sensitive; a flip-flop is commonly edge-triggered. A clock coordinates state transitions but does not eliminate setup, hold, propagation or clock-skew constraints.

An expanded state table lists current state, inputs, next state and outputs. Counter modulus is the number of states in its cycle. A decimal counter has modulus 10. A ring counter circulates a pattern through a register and trades extra storage for simple state decoding.

Sequential correctness requires both logical next-state equations and valid timing. A design that has the right state table can still fail physically if its clock period or setup/hold requirements are violated.

Unit 16: Oscillators, Multivibrators, Timers, and the Transition to PWM

16.1. Stable and quasi-stable States

Multivibrators form an important class between analog timing and digital state behavior. A bistable circuit has two stable states and changes state in response to an external event. A monostable circuit has one stable state; after triggering it enters a temporary state for a defined interval and then returns. An astable circuit has no stable state and oscillates continuously to generate a periodic square or pulse waveform.

This distinction is useful beyond the 555 timer; it also appears in watchdogs, pulse stretchers, debounce circuits, clocks, and timeout logic.

16.2. Creating Time with RC Behavior

When a capacitor charges through a resistor:

v_C(t)=V_S(1-e^(-t/RC))

and during discharge:

v_C(t)=V_0e^(-t/RC)

is a useful ideal model. Timer circuits compare this continuous voltage with defined thresholds and convert it into a digital state transition.

16.3. Functional Structure of the NE555

The NE555 is not merely an RC network. Functionally it combines:

resistor divider
   ↓
two comparators
   ↓
SR latch
   ↓
output stage
   +
discharge transistor

The internal divider establishes reference levels near V_CC/3 and 2V_CC/3. Trigger and threshold inputs change the latch state relative to those levels, while the discharge transistor controls the timing capacitor's discharge path.

16.4. Monostable Operation

In monostable operation, a trigger drives the output into a temporary active state. When the capacitor reaches the threshold, the circuit returns to its stable state. For the classic ideal connection, pulse duration scales approximately as:

t ≈ 1.1RC

This mode is useful for one-shot pulses, timeout generation, and pulse stretching.

16.5. Astable Operation

In astable operation, the timing capacitor continuously charges and discharges between two thresholds, creating a periodic output. For the classic two-resistor connection:

f ≈ (1.44)/((R_A+2R_B)C)

is a common approximation.

Frequency and duty cycle are not independent in the classic topology. Separating charge and discharge paths with diodes is one way to obtain a wider duty-cycle range. Real frequency also depends on resistor, capacitor, supply, and internal-threshold tolerances.

16.6. Bistable Operation

Without a timing capacitor, set/reset-like control of the internal latch can provide bistable behavior. This illustrates that the comparator-latch structure inside the 555 is more general than an oscillator alone.

16.7. Control and Reset Inputs

The control-voltage input allows the internal threshold levels to be modified externally. Appropriate bypassing can reduce false triggering in electrically noisy environments.

The reset input forces a defined state. Startup and fault-state behavior should therefore be treated as part of the circuit design rather than left to an undefined node.

16.8. From Square Wave to PWM

For a periodic pulse waveform:

D=(t_on)/(T)

defines duty cycle. Varying duty controls the fraction of each period during which energy is applied to a load.

The signal and harmonic interpretation of PWM belongs to Signals and Systems, hardware timer/PWM generation to Microprocessors, and the power-switching stage to Power Electronics.

16.9. Logic Output and Power Switch Are Different Layers

A 555 or microcontroller output should not automatically be treated as a direct power-load driver. When a power MOSFET gate is driven, the device's specified gate-drive voltage, gate charge, R_(DS(on)), drain-source voltage/current limits, and thermal limits must be evaluated together.

MOSFET V_(GS(th)) is not the gate voltage required for low-loss full enhancement. A non-logic-level device such as the IRFZ44N may begin conducting at a low gate voltage yet still have excessive resistance at substantial load current.

16.10. Transition to an Inductive Load

A 555-to-MOSF DC-motor example should be divided by engineering responsibility:

NE555 timing / PWM
    -> this course

MOSFET gate drive + flyback + transient control
    -> Power Electronics

motor current / torque / speed behavior
    -> Actuators, Electrical Machines and Drive Systems

feedback speed / position control
    -> Automatic Control

This separation prevents the same circuit from being retaught in several courses while keeping the physical responsibility of each subject clear.

References

• Adel S. Sedra; Kenneth C. Smith. Microelectronic Circuits. Oxford University Press, 2010.

• Celozzi, Salvatore; Araneo, Rodolfo; Lovat, Giampiero. Electromagnetic Shielding. Wiley-IEEE Press, 2008. ISBN 978-0-470-05536-6.

• James W. Nilsson; Susan A. Riedel. Electric Circuits. Pearson, 2011.

• M. Morris Mano; Michael D. Ciletti. Digital Design. Pearson, 2012.

• Mor Harchol-Balter. Performance Modeling and Design of Computer Systems: Queueing Theory in Action. Cambridge University Press, 2013.

• Pete Warden, D. S. TinyML: Machine Learning with TensorFlow Lite on Arduino and Ultra-Low-Power Microcontrollers. O’Reilly Media, 2019.

• Peter J. Huber; Elvezio M. Ronchetti. Robust Statistics. 2nd ed. Wiley, 2009.

• Robert L. Boylestad; Louis Nashelsky. Electronic Devices and Circuit Theory. Pearson, 2012.