Interrupt Latency
The delay between an interrupt becoming pending and execution of its corresponding interrupt service routine actually beginning.
What Contributes to the Delay?
Interrupt latency is more than the processor noticing an interrupt. Higher-priority interrupts, masking, critical sections, completion of current instructions, context save, cache/TLB effects and kernel policy can all delay the start of the handler.
For real-time systems, average latency is often insufficient. Deadline analysis is more concerned with a defensible upper bound and jitter.
Measurement
Software timestamps may not expose the full hardware path. On appropriate embedded systems, toggling a GPIO and measuring with an oscilloscope or logic analyzer can directly observe the interval between an external interrupt event and the first visible ISR action.
Relationship with the ISR
Once the handler starts, an unnecessarily long ISR can delay other interrupts and lower-priority work. Interrupt Service Routines are therefore normally kept bounded.