Microprocessors

Microprocessors provide a compact way to study computer architecture because the relationship between instruction execution, registers, buses, memory, interrupts, and peripheral interfaces is directly visible. The Intel 8085 and 8086 are historically old devices, but many of the architectural concepts they expose remain relevant to embedded systems and modern processors.

Unit 1: Fundamental Concepts

A microprocessor integrates a programmable processing core, including arithmetic/logic, registers, and control logic. In the traditional 8085/8086 distinction, main memory and peripherals are external. Modern microprocessors may integrate caches, memory controllers, interconnects, accelerators, and other system functions.

A microcomputer combines a microprocessor with memory and input/output facilities. A microcontroller integrates the processing core, memory, and peripherals for embedded control.

A processor repeatedly performs:

fetch → decode → execute

The program counter identifies the next instruction. Instruction execution may read operands, modify registers or memory, update status flags, and redirect control flow.

Machine code is the binary representation consumed by the processor. Assembly language provides symbolic mnemonics, labels, expressions, and assembler directives that are translated into machine code.

Unit 2: 8085 Architecture

The 8085 is an 8-bit processor with a 16-bit address bus and a 64 KiB address space.

Important programmer-visible registers include:

Main programmer-visible registers of the 8085:

• A, 8 bit: Accumulator used as a primary operand and result register for arithmetic and logical operations.
• B, C, D, E, H, and L, 8 bit: General-purpose registers. BC, DE, and HL can also be used as 16-bit register pairs.
• PC, 16 bit: Program counter holding the address of the next instruction.
• SP, 16 bit: Stack pointer identifying the top of the stack.
• Flags, 8 bit: Processor-status register containing Sign, Zero, Auxiliary Carry, Parity, and Carry state.

BC, DE, and HL can be used as 16-bit register pairs. HL is also used as a memory pointer; the symbolic operand M refers to the byte addressed by HL.

The status flags are Sign, Zero, Auxiliary Carry, Parity, and Carry. Flag effects are instruction-specific. INR and DCR do not modify Carry; INX and DCX do not modify flags; DAD affects Carry.

Multiplexed address/data bus

AD0–AD7 carry the low address byte during the first part of a machine cycle and data later in the cycle. ALE allows external hardware to latch the low address. A8–A15 carry the high address byte.

Control signals such as RD, WR, IO/M, S0, and S1 identify bus operations. READY allows slower devices to insert wait states.

Unit 3: Instruction Set and Addressing

8085 instructions may be one, two, or three bytes long. Multi-byte immediate data and addresses use little-endian byte ordering.

Instruction groups include data transfer, arithmetic, logical operations, branches, stack operations, machine control, and input/output.

Addressing modes include register, immediate, direct, register-indirect, and implied addressing. Understanding the effective address and the number of memory accesses is essential when analyzing timing.

Unit 4: Timing and Machine Cycles

Instruction time is built from T-states and machine cycles. An opcode fetch, memory read, memory write, I/O read, and I/O write have distinct bus behavior.

A software delay loop derives timing from the exact instruction path:

delay ≈ Σ(instruction T-states) × clock period

Branches make loop timing path-dependent. Interrupts can add jitter, so software delay loops are unsuitable when strict timing must coexist with asynchronous events.

Unit 5: Stack and Subroutines

The stack is a LIFO structure addressed through SP. On the 8085 the stack grows toward lower addresses.

CALL saves the return address and transfers control to a subroutine. RET restores the return address. PUSH and POP transfer register-pair data to and from the stack.

Stack correctness depends on balanced operations and valid stack memory. Interrupt handlers and nested calls increase the maximum required stack depth.

Unit 6: Memory and Interfacing

A memory map assigns regions of the processor address space to physical devices. Address decoding determines which chip responds to a bus cycle.

The 8085 supports isolated I/O through IN and OUT, using an 8-bit port address. Devices may alternatively be memory-mapped, allowing ordinary memory instructions to access them at the cost of consuming memory address space.

Incomplete address decoding can create aliases in which the same physical device responds at multiple addresses.

Unit 7: Interrupts

Polling repeatedly checks device state and consumes processor time. Interrupts allow a peripheral or event to request service asynchronously.

The 8085 interrupt inputs include TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. They differ in priority, maskability, vectoring, and trigger behavior.

TRAP is non-maskable. RST 7.5 is edge-triggered and latched. RST 6.5 and RST 5.5 are level-sensitive. INTR is non-vectored and requires an interrupt-acknowledge exchange.

SIM controls interrupt masks and the serial output function; RIM reads mask, pending-interrupt, global interrupt-enable, and serial-input state.

Interrupt latency is the interval between the request and execution of the handler. Critical real-time systems must account for instruction completion time, higher-priority handlers, masking intervals, and handler prologue overhead.

Unit 8: Serial Communication

Parallel transfer uses multiple data lines; serial transfer sends bits over fewer lines. Asynchronous serial communication requires an agreed bit rate and framing, typically start, data, optional parity, and stop bits.

The 8085 provides simple SID and SOD pins controlled through RIM and SIM. Software must implement bit timing, so dedicated USART/UART hardware is preferable for reliable communication and lower CPU load.

Electrical standards such as RS-232 define signaling characteristics and should not be confused with higher-level framing or application protocols.

Unit 9: Parallel I/O and the 8255A

The 8255A Programmable Peripheral Interface provides configurable parallel ports.

Its modes support basic input/output and handshaked transfers. Handshaking coordinates producer and consumer when their timing is not inherently synchronized.

The control word determines port direction and operating mode. Correct interface design must consider both logical protocol and electrical loading.

Unit 10: Programmable Timers and Counters

The 8253/8254 family provides three independent programmable 16-bit counters. Each channel has clock, gate, and output signals.

Operating modes support terminal count, rate generation, square-wave generation, hardware-triggered strobes, and related timing functions. The 8254 adds read-back functionality.

Hardware timers provide more deterministic timing than processor delay loops because the counter progresses independently of ordinary instruction execution.

Unit 11: Data Transfer Schemes

Programmed I/O

The CPU explicitly polls and transfers each data item. The design is simple but wastes processor cycles.

Interrupt-driven I/O

The device interrupts when service is required. CPU utilization improves, but every transfer still involves interrupt and software overhead.

Direct Memory Access

DMA transfers data between a peripheral and memory without routing every data word through ordinary CPU instructions. On classic bus-based systems a DMA controller requests bus ownership with HOLD, and the processor acknowledges with HLDA.

DMA improves throughput for block transfers but introduces bus arbitration, cache-coherency, ordering, buffer ownership, and synchronization issues in modern systems.

Unit 12: 8086 and the Transition to 16 Bits

The 8086 has a 16-bit data path and a 20-bit address space. Its Bus Interface Unit and Execution Unit allow instruction prefetch to overlap with execution.

Segment registers CS, DS, SS, and ES participate in physical address formation:

physical address = segment × 16 + offset

The segmented model allows a 16-bit offset to participate in addressing a 1 MiB physical space, but creates aliasing and software complexity.

String instructions use SI, DI, and the Direction Flag. REP prefixes repeat operations under control of CX.

Unit 13: Classical Concepts in Modern Architectures

CISC and RISC

CISC and RISC describe design tendencies rather than a strict modern binary classification. Contemporary processors often decode complex architectural instructions into simpler internal operations.

Pipelining

Pipelining overlaps stages of different instructions. Ideal throughput is limited by data, control, and structural hazards. Forwarding, speculation, branch prediction, out-of-order execution, and duplicated resources mitigate these hazards but increase complexity.

For hard real-time systems, mechanisms that improve average throughput can complicate worst-case execution-time analysis.

Cache and memory hierarchy

Modern systems bridge the latency gap between CPU and main memory using multiple cache levels. Locality is therefore a performance property of software as well as hardware.

Interrupt controllers and DMA

Modern interrupt controllers support prioritization, routing, affinity, and large interrupt spaces. DMA engines support scatter/gather, circular buffers, peripheral triggers, and memory-to-memory transfers.

Protection and security

Privilege levels, memory protection, MMUs/MPUs, execute permissions, isolation, and virtualization extend the simple memory-map concept into system-wide protection mechanisms.

Multicore systems

Multiple cores introduce concurrency and memory-consistency concerns. Cache coherence, atomic operations, memory ordering, locks, and lock-free algorithms become part of processor-level programming.

Core Concepts and Quick Reference

The enduring architectural chain is:

instruction
→ registers
→ datapath
→ bus transaction
→ memory or peripheral
→ timing
→ interrupt/DMA interaction
→ system-level concurrency

Studying classic processors is useful because these mechanisms are visible without the layers of speculation, cache hierarchy, and out-of-order execution present in modern high-performance CPUs.

References

• Intel. 8080/8085 Assembly Language Programming Manual.
• Intel. 8086 Family User's Manual.
• Intel. 8255A Programmable Peripheral Interface documentation.
• Intel. 8253/8254 Programmable Interval Timer documentation.
• Patterson, D. A., Hennessy, J. L. Computer Organization and Design.