Race Condition
A correctness defect where the outcome depends on uncontrolled relative timing between concurrent operations and changes across possible interleavings.
Timing-Dependent Correctness
A race condition exists when multiple execution contexts interact with shared state and correctness depends on which operation happens first.
The problem is not simply that two threads run concurrently; it is that an invalid interleaving is possible.
Not Identical to a Data Race
Some language and memory models define data race more narrowly. A higher-level check-then-act race can still exist even when individual accesses use locks or atomics.
Testing Difficulty
The failure may require a narrow scheduling window and can disappear for long periods. Logging or attaching a debugger can change timing enough to hide it.
Robust solutions reduce shared mutable state, define the correct atomicity boundary and make valid state transitions explicit.
Related Concepts
- Deadlock
- Compare-and-Swap
- Memory Barrier
- Thread Safety