Digital Logic Design

The material progresses from Boolean expressions to physical combinational circuits and then to sequential behavior and state machines. Karnaugh maps, arithmetic blocks, flip-flops, counters, and registers form a continuous design chain. HDL terminology is included where it helps explain the same underlying hardware concepts.

Unit 1: Number Systems and Binary Codes

1.1. Positional Number Systems

A positional number system represents a number as weighted digits. For radix r, the value of digits d_i is:

N = sum(d_i * r^i)

The rightmost integer digit has weight r^0, the next r^1, and fractional positions use negative powers.

1.2. Number of Combinations

With n independent binary positions there are:

2^n

different bit patterns. This relation is fundamental when selecting the number of bits required to represent states, codes, addresses or unsigned magnitudes.

1.3. Decimal, Binary, Octal and Hexadecimal

Decimal uses radix 10; binary radix 2; octal radix 8; hexadecimal radix 16. Octal and hexadecimal are convenient compact representations of binary because one octal digit maps to three bits and one hexadecimal digit maps to four bits.

To convert an integer from decimal to binary, repeated division by two can be used and remainders read in reverse order. To convert binary to decimal, sum the powers of two corresponding to set bits. Fractional conversion can be performed by repeated multiplication for the target radix, noting that some decimal fractions have non-terminating binary expansions.

1.4. Binary Arithmetic

Binary addition follows:

0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10
1 + 1 + 1 = 11

Subtraction can be performed directly or by addition using two's-complement representation.

For an n-bit two's-complement value, negation is obtained by complementing the bits and adding one, provided the mathematical result is representable. The range is:

-2^(n-1) ... 2^(n-1)-1

Unsigned carry and signed overflow are different concepts. In two's-complement addition, overflow occurs when operands with the same sign produce a result with the opposite sign.

Binary multiplication is based on shifted partial products. Binary division follows the same quotient/remainder principle as long division, implemented in hardware through shifts, subtraction and control.

1.5. Binary Values and Binary Codes

A bit pattern can represent a number, character, state, instruction or control field. A binary code assigns bit patterns to symbols or values according to a convention; the pattern itself does not determine its meaning.

BCD encodes each decimal digit separately in four bits. For example, decimal 59 is encoded as:

0101 1001

not as the pure binary representation of fifty-nine.

Alphanumeric encodings such as ASCII map character symbols to numeric codes. The logic circuit handles bits; interpretation belongs to the encoding convention.

1.6. Signed Representations: sign-magnitude, One's Complement, and Two's Complement

Several encodings have historically been used for signed integers.

In sign-magnitude, the most significant bit carries the sign and the remaining bits carry magnitude. It is intuitive but creates both +0 and -0.

In one's complement, a negative value is formed by inverting all bits of the positive representation. It also has two zero encodings.

In two's complement, there is one zero representation and the same adder structure can be used naturally for positive and negative arithmetic. It is therefore the dominant signed-integer representation in modern general-purpose digital systems.

For n bits:

unsigned range:
0 ... 2^n - 1

two's-complement signed range:
-2^(n-1) ... 2^(n-1) - 1

The same bit pattern can mean different values under different interpretations. For eight bits, 11111111 is 255 as unsigned data and -1 in two's complement.

A bit pattern and its numeric interpretation are therefore separate concepts.

1.7. Carry versus Signed Overflow

Carry is primarily associated with unsigned arithmetic. Signed overflow indicates that the mathematical result cannot be represented in the selected two's-complement width.

For four signed bits:

0111 = +7
0001 = +1
-----------
1000

the bit-level addition completes, but +8 is outside the four-bit signed range.

Carry and signed overflow are not interchangeable status conditions.

1.8. Gray Code

Adjacent Gray-code words differ by one bit. This property is useful in position encoders and in selected clock-domain-crossing structures where changing several binary bits at once would create additional sampling ambiguity.

Binary-to-Gray conversion can be written as:

gray = binary XOR (binary >> 1)

For three bits:

binary  000 001 010 011 100 101 110 111
gray    000 001 011 010 110 111 101 100

Gray code is a coding scheme rather than an arithmetic number system.

1.9. Excess-3 and Decimal Codes

Excess-3 (XS-3) adds 3 to each decimal digit and encodes the result in four binary bits.

0 -> 0011
5 -> 1000
9 -> 1100

The code is historically important and helps illustrate why decimal codes such as BCD and XS-3 are different from pure binary numeric representation.

1.10. Fixed-point Representation

In fixed-point representation, the position of the binary point is part of the design contract.

In an eight-bit format such as Q4.4, some bits are interpreted as integer significance and the remaining bits as fractional significance.

The hardware still stores an ordinary bit vector; the scale belongs to the interpretation. Fixed-point arithmetic can provide compact, predictable hardware cost compared with floating point, but range and scaling become explicit design responsibilities.

1.11. Reading Digital Design Through Correctness, Timing, and Hardware Reality

The subjects form a continuous abstraction chain:

number representation
        ↓
Boolean algebra
        ↓
logic gates
        ↓
combinational blocks
        ↓
storage elements
        ↓
registers and counters
        ↓
finite-state machines
        ↓
processor datapaths and control

The important connection is that processor-scale structures are built from the same principles introduced by basic logic gates. Boolean simplification controls combinational cost; timing and state determine sequential correctness; encoding determines how abstract information becomes bits. Digital design is therefore not a collection of unrelated gate symbols but a hierarchy from representation to stateful computation.

1.12. Connection to Mechanical Computation

My examination of a FACIT mechanical calculator provides a historical non-electronic comparison for arithmetic state, carry and digit mechanisms discussed in digital logic.

Unit 2: Binary Logic and Logic Gates

2.1. Binary Logic

Binary logic operates on variables whose logical values are conventionally represented as 0 and 1. Physical voltage ranges implement these values according to the chosen logic family; logic levels are abstractions, not exact universal voltages.

2.2. AND, OR and NOT

AND is true only when all required inputs are true:

A B | A AND B
0 0 |    0
0 1 |    0
1 0 |    0
1 1 |    1

OR is true when at least one input is true. NOT complements its input.

A switching model helps connect Boolean algebra to circuits: series switches resemble AND behavior, while parallel switches resemble OR behavior.

2.3. Buffer and Inverter

A buffer preserves the logical value while providing electrical isolation, drive capability or timing function. An inverter implements NOT.

2.4. NAND and NOR

NAND and NOR are universal gates. Any Boolean function can be implemented using only NAND gates or only NOR gates. This is important in logic synthesis and historically useful for implementation with a limited gate family.

2.5. XOR and XNOR

XOR is true when its inputs differ; XNOR is true when they are equal. XOR appears in adders, parity logic and bit toggling. For two inputs:

A XOR B = A'B + AB'

Unit 3: Analysis and Synthesis of Logic Circuits

Combinational circuit synthesis begins by defining the meaning of inputs and the cases that may legitimately be unspecified. Convert the truth table to Boolean functions and recheck functional equivalence after simplification. Fewer gates do not automatically make a better circuit: critical-path delay, fan-out, and transient hazards also matter. Evaluate the implementation against target technology and timing requirements.

3.1. Analysis

Circuit analysis starts from a known logic diagram and derives its Boolean expression, truth table and input/output behavior. Intermediate nodes can be named and evaluated step by step.

3.2. Synthesis

Synthesis starts from a required behavior, usually a truth table or Boolean specification, and constructs a circuit. Typical steps are:

1. define inputs and outputs,
2. derive the truth table,
3. write a Boolean expression,
4. simplify the expression,
5. map the result to available gates.

3.3. Minterms and Sum of Products

A minterm is a product term containing every input variable exactly once, either complemented or uncomplemented. It is true for exactly one row of the truth table.

A Boolean function can be expressed canonically as the OR of the minterms for which its output is 1:

F = Sigma m(...)

A simplified sum-of-products expression need not contain every variable in every product term.

3.4. Maxterms and Product of Sums

A maxterm is a sum term that is false for exactly one input combination. A function can be represented as the AND of the maxterms corresponding to its zero rows:

F = Pi M(...)

Canonical SOP/POS forms are systematic; simplified forms are used to reduce implementation cost.

3.5. From Truth Tables to Timing Behaviour

Logical correctness and timing correctness are separate properties of a digital circuit. In combinational logic, outputs depend only on current inputs. Sequential logic also depends on stored state, so a flip-flop, counter, or state machine cannot be fully described by a truth table without clocking and timing assumptions.

Boolean simplification aims to reduce gate count or logic depth without changing the function. Karnaugh-map grouping uses power-of-two groups, with opposite edges treated as adjacent. Larger legal groups often produce simpler expressions, but every required 1 cell still has to be covered.

A half adder combines two bits; a full adder also accepts a carry from the previous position. In a multi-bit ripple-carry adder, carry propagation through successive stages creates the critical delay. More advanced carry structures reduce this path rather than changing the arithmetic definition.

Setup and hold times describe intervals around a clock edge during which a flip-flop input must remain stable. Violating them can create metastability risk. A synchroniser chain can be appropriate for a single control bit crossing clock domains, but synchronising the bits of a multi-bit word independently does not guarantee a coherent transferred word.

For a finite-state machine, state encoding, transition logic, and output logic should be read separately. Moore outputs depend only on state; Mealy outputs can depend on both state and current input. The distinction affects response timing and possible transient output behaviour.

Unit 4: Boolean Algebra

4.1. Basic Identities

Boolean algebra provides identities such as:

A + 0 = A
A * 1 = A
A + 1 = 1
A * 0 = 0
A + A = A
A * A = A
A + A' = 1
A * A' = 0
(A')' = A

Commutative, associative and distributive laws support algebraic transformation. Absorption includes:

A + AB = A
A(A + B) = A

4.2. De Morgan's Laws

(A B)' = A' + B'
(A + B)' = A' B'

These identities are central when converting logic to NAND-only or NOR-only forms.

4.3. NAND-only and NOR-only Implementation

A two-level SOP implementation naturally maps to NAND-NAND form by applying De Morgan transformations. POS similarly maps naturally to NOR-NOR form. Correct bubble placement and inversion accounting are more important than memorizing a drawing pattern.

Unit 5: Karnaugh Maps

When grouping a Karnaugh map, verify that adjacent cells differ in one bit and account for wraparound adjacency. Covering required ones with suitably large power-of-two groups reduces common terms, but every required one must be included. If several minimal expressions exist, compare timing and hazard behavior. Equivalence to the original truth table remains the final functional check.

5.1. Purpose

A Karnaugh map places truth-table cells so that adjacent cells differ in only one variable. This Gray-code ordering makes algebraic adjacency visible and allows implicants to be grouped geometrically.

5.2. Two-, three- and four-variable Maps

The map contains 2^n cells for n variables. Rows and columns must use Gray ordering, for example:

00 01 11 10

rather than ordinary binary order.

5.3. Grouping Rules

For SOP simplification, group 1 cells in rectangles whose sizes are powers of two:

1, 2, 4, 8, ...

Groups may wrap across map edges because the first and last rows/columns are logically adjacent. Larger valid groups remove more variables. Overlap is allowed when it produces a simpler cover.

For POS, group zero cells instead.

5.4. Don't-care Conditions

Input combinations that cannot occur or whose output is irrelevant may be marked as don't-care. They can be treated as 0 or 1 independently to obtain a simpler circuit, but only when the system specification truly permits either output.

5.5. Limits

Karnaugh maps are convenient for small variable counts. Algorithmic minimization and synthesis tools are better for large designs; a K-map is a teaching and manual-design aid rather than a scalable industrial optimizer.

Unit 6: Combinational Circuit Design

6.1. Design Process

A combinational circuit has outputs determined by current inputs only. A disciplined design process is:

1. define input/output meaning,
2. form the truth table,
3. derive output functions,
4. simplify,
5. implement and verify.

6.2. Half Adder

A half adder adds two bits:

S = A XOR B
C = A B

It has no carry input.

6.3. Full Adder

A full adder adds A, B and carry-in Cin:

S = A XOR B XOR Cin
Cout = AB + ACin + BCin

It can be constructed from two half adders and an OR gate.

6.4. Parallel Adder

Cascading full adders creates a multi-bit ripple-carry adder. Carry propagates from lower to higher positions, so the worst-case delay grows with word width. Faster architectures reduce carry propagation through lookahead, prefix or related structures.

6.5. Subtraction with Two's Complement

An adder can perform subtraction:

A - B = A + (~B + 1)

Hardware often uses a control signal to conditionally complement B and supply the initial carry-in, allowing one adder structure to support addition and subtraction.

6.6. Ripple-carry Delay and Faster Carry Structures

A multi-bit parallel adder can be built by cascading full adders. In the simplest implementation, one stage's carry output drives the next stage's carry input:

C0 -> FA0 -> C1 -> FA1 -> C2 -> FA2 -> ...

This ripple-carry structure is functionally correct, but the most significant result can depend on carry propagation through many stages.

Carry generate and propagate terms can be written as:

G_i = A_i B_i
P_i = A_i XOR B_i
C_(i+1) = G_i + P_i C_i

so that parts of the carry relation can be evaluated in parallel. Carry-lookahead and related structures do not change arithmetic semantics; they change circuit structure to reduce the critical path.

6.7. Adder-subtractor

The same n-bit adder can support both addition and subtraction with a control input.

SUB = 0:
B' = B
Cin = 0

SUB = 1:
B' = NOT(B)
Cin = 1

This implements both A + B and two's-complement subtraction A - B through the same carry network.

6.8. BCD Correction

A BCD digit uses only 0000 through 1001. If four-bit binary addition produces a value above 1001, or produces a decimal carry, the digit must be corrected.

A classic correction adds:

0110

to restore a valid BCD digit and propagate the decimal carry.

This illustrates the difference between arithmetic hardware and code semantics: a binary adder can be electrically correct while additional logic is required to preserve a decimal code.

6.9. Comparators

A magnitude comparator produces relations such as:

A < B
A = B
A > B

Multi-bit comparison proceeds from the most significant unequal position. Cascaded comparator blocks propagate higher-order equality/greater/less information through lower groups.

Unit 7: Encoders and Decoders

7.1. Encoder

An encoder maps one-of-many asserted input lines to a compact binary code. A simple encoder assumes only one input is active.

A priority encoder resolves multiple simultaneous active inputs by assigning a defined priority, often also providing a valid indicator.

7.2. Decoder

A decoder maps an n-bit code to up to 2^n output lines. For a 2-to-4 decoder, exactly one output corresponds to each binary input combination when enabled.

Enable inputs are useful for cascading decoder blocks and for controlling when outputs participate in a larger circuit.

Decoders can implement Boolean functions by OR-ing the minterm outputs corresponding to desired truth-table rows.

7.3. Priority Encoders, Enable Signals, and Scalable Decoding

A simple encoder assumes that only one input is active. A priority encoder defines which input wins when several inputs are asserted. This makes the circuit suitable for interrupt prioritization and arbitration-like problems.

Decoder enable inputs allow larger decoders to be built hierarchically. The enable path is also part of timing: a logically correct decoded output may still violate a downstream setup requirement if enable and address paths have different delays.

Multiplexers can implement arbitrary Boolean functions by mapping variables to select lines and constants or literals to data inputs. This makes them useful as both routing elements and logic-building blocks.

7.4. Code Converters and Display Decoders

A code converter maps the same information between coding schemes.

Examples include:

binary -> Gray
Gray -> binary
BCD -> seven-segment

Unused input patterns matter. If they are physically impossible by contract, they may be treated as don't-care conditions for simplification. If they can occur, the design should define a safe output rather than relying on an unspecified combination.

7.5. Seven-segment Display

A seven-segment display forms decimal symbols from combinations of segments a...g.

A BCD-to-seven-segment decoder follows:

BCD digit
   ↓
decoder
   ↓
a b c d e f g

Common-anode and common-cathode displays can require opposite active levels, so the truth table must specify whether an output is active-high or active-low.

Multi-digit displays are often multiplexed by sharing segment lines and enabling one digit at a time. Scan frequency, drive current, and duty cycle then become part of the physical design.

Unit 8: Multiplexers, Demultiplexers and Three-State Logic

8.1. Multiplexer

A multiplexer selects one of several data inputs according to select lines. A 2-to-1 multiplexer implements:

Y = S' I0 + S I1

A 4-to-1 multiplexer uses two select bits. Multiplexers can also implement arbitrary Boolean functions by assigning variables to select lines and constants/subexpressions to data inputs.

8.2. Demultiplexer

A demultiplexer routes one data input to one selected output. Decoder and demultiplexer structures are closely related but differ in how the data/enable input is interpreted.

8.3. Three-state Output

A three-state output can be logical 0, logical 1, or high impedance Z. High impedance allows a device to disconnect electrically from a shared line.

Tri-state buses were historically common for board-level and some internal bus structures. Modern FPGA internal routing generally maps logical tri-state descriptions into multiplexer networks, while physical I/O pins can still provide real three-state behavior.

Unit 9: Parity Circuits and the Arithmetic Logic Unit

9.1. Parity

Parity adds one redundant bit for simple error detection. With even parity, the total number of 1 bits is even; with odd parity it is odd.

XOR networks naturally generate parity:

P = A XOR B XOR C XOR ...

A single parity bit detects any odd number of bit inversions but cannot correct errors and does not detect every even-numbered error pattern.

9.2. Arithmetic Logic Unit

An ALU combines arithmetic and logical operations under function-selection controls. Typical operations include:

• addition,
• subtraction,
• AND,
• OR,
• XOR,
• shifts or pass-through operations depending on the design.

The ALU normally also produces status information.

9.3. Status Flags

Common flags include:

• zero: result is zero,
• sign/negative: typically derived from the most significant result bit for signed interpretation,
• carry: unsigned carry/borrow-related information,
• overflow: signed arithmetic result is not representable,
• parity: parity of a selected result field in architectures that define it.

Carry and signed overflow must not be confused.

9.4. From Digital Logic to AI Accelerators

An AI accelerator is still a digital circuit. Matrix multiplication, convolution, and attention eventually reduce to Boolean logic, registers, adders, multipliers, multiplexers, control, and memory structures. The connection between digital logic and AI therefore comes from mapping computation to physical circuits, not from the learning theory itself.

A common neural-network primitive is multiply-accumulate:

acc = acc + w * x

A layer may repeat this operation millions of times. A general-purpose processor executes it through an instruction stream; a domain-specific accelerator may place many MAC units in parallel and organize dataflow around them. The design problem is not simply to build a faster multiplier, but to feed many arithmetic units efficiently.

Systolic arrays illustrate the idea. Data moves through a regular grid of processing elements; each element performs local multiply-accumulate operations while weights and activations are reused. The basic elements remain familiar:

register
+ combinational arithmetic
+ control
+ local data movement

Bit width directly affects the design. INT8 arithmetic can reduce storage and allow more parallel units than wider floating-point formats, but changes range and numerical error. Saturation, sign handling, rounding, and overflow become system-level properties because they may alter model output.

Activation functions create different hardware costs as well. A function approximable by comparisons and additions is not equivalent to a high-accuracy implementation requiring exponentiation or division. Algorithm and circuit cannot be selected independently when latency, power, or silicon area is constrained.

Memory is often the dominant limitation. If weights repeatedly travel from external memory, arithmetic units may stall and energy cost can be dominated by movement rather than multiplication. Register files, SRAM buffers, banking, and reuse strategies are therefore central to accelerator design.

FPGA inference provides another direct example. Selected model operators can be mapped into fixed data paths and pipelines. The advantage comes from reconfiguring digital hardware around an application-specific flow, not from executing the same instruction stream as a CPU.

Digital logic does not form the mathematical foundation of AI. It forms the implementation layer through which AI computation becomes parallel, bounded-latency, and energy-aware hardware.

Unit 10: Sequential Logic Circuits

10.1. State

Unlike a combinational circuit, a sequential circuit's output can depend on both current inputs and stored state. Memory elements therefore become part of the logical model.

10.2. Latches

An SR latch can be constructed from cross-coupled NOR or NAND gates. Its set, reset and hold behavior depends on the chosen active-high or active-low implementation. One input combination is forbidden or problematic in the basic form.

A gated latch adds an enable condition. A D latch removes the ambiguous S/R command pair by deriving set/reset behavior from one data input.

10.3. Flip-flops

A flip-flop samples according to a clock event rather than being transparent throughout an enable level. Common types include:

• SR,
• D,
• T,
• JK.

A D flip-flop stores the sampled value of D. A T flip-flop toggles when enabled. A JK flip-flop generalizes SR behavior and toggles for the appropriate J/K combination.

10.4. Clock Edge, Setup and Hold

Edge-triggered storage requires input timing around the active clock edge. Setup time is the interval for which data must be stable before the edge; hold time is the interval it must remain stable afterward.

Violating these constraints can lead to metastability. A logical simulation that ignores analog timing does not remove this physical limitation.

10.5. Master-slave Concept

A traditional master-slave arrangement uses complementary phases/levels of storage elements to obtain edge-like behavior. Modern standard-cell flip-flops can be implemented differently internally, but the model remains useful for understanding why state updates are synchronized.

10.6. Asynchronous Preset and Clear

Many flip-flops provide asynchronous set or clear inputs that override normal data/clock behavior without waiting for a clock edge.

Typical uses include initialization, forcing a known safe state, and selected control sequences.

The active level must be read from the symbol and device specification.

Release of an asynchronous reset is also a timing problem. Deassertion near a clock edge can violate recovery/removal requirements. A common synchronous-design pattern is therefore:

asynchronous assert
synchronous deassert

with the final strategy determined by the target technology and system requirements.

10.7. Characteristic Tables versus Excitation Tables

Two different table types should not be confused.

A characteristic table maps current state and input to next state.

An excitation table maps current state and required next state to the input values needed to cause that transition.

Excitation tables are particularly useful when synthesizing state machines with JK, T, or SR flip-flops.

For a D flip-flop:

D = Q(next)

so the mapping is direct.

10.8. Clock-to-Q, Recovery, and Removal

Setup and hold are not the only timing parameters.

Clock-to-Q is the delay from the active clock edge until the flip-flop output reaches the new value. It is part of a synchronous critical-path budget.

Asynchronous set/reset pins also have recovery and removal requirements that constrain their timing relative to the clock.

The statement that a flip-flop changes "instantly" at a clock edge is therefore an idealized logical model rather than a physical fact.

Unit 11: Synchronous Counter Design

11.1. Counters

A counter is a sequential circuit whose states follow a defined sequence. A modulo-m counter cycles through m distinct states.

The minimum number of state bits is:

ceil(log2(m))

although unused binary states may exist and should have defined recovery behavior when reliability matters.

11.2. Synchronous and Ripple Counters

In a ripple counter, one flip-flop output clocks another, so transition delay accumulates through the chain. In a synchronous counter, all state flip-flops share a clock and combinational logic determines the next state. Synchronous design is easier to time predictably at higher frequencies.

11.3. Decimal and Ring Counters

A decimal/BCD counter cycles through ten valid states. The six unused four-bit states should be considered in the next-state design rather than assumed impossible forever.

A ring counter circulates a one-hot or patterned bit through a shift register. It uses more flip-flops than a binary counter for the same number of states but can simplify decoding.

11.4. Timing

A synchronous design must satisfy propagation, setup, hold and clock-distribution constraints. The logical next-state function may be correct while the physical circuit still fails timing.

11.5. Ring and Johnson Counters

A ring counter circulates a bit pattern through a shift register. With a one-hot representation, n flip-flops can provide n easily decoded states.

A Johnson counter feeds the inverted final bit back to the first stage and can ideally produce 2n states from n flip-flops.

These structures are less bit-efficient than binary counters but can simplify state decoding.

11.6. Programmable Modulus and Terminal Count

A counter does not have to use all 2^n binary states.

A modulo-m design follows:

0 ... m-1

and then returns to its initial state.

Unused encodings should have defined recovery behavior when reliability matters:

illegal state -> known valid state

Terminal-count or carry outputs can be used to cascade counters or trigger another block at a boundary condition.

11.7. Separate Frequency Division from Timing Correctness

Each stage of an ideal binary counter divides frequency by two, but outputs of a ripple counter do not change simultaneously.

If several ripple-counter bits are decoded together, transient combinations may appear during propagation.

Frequency division, state encoding, and timing correctness are therefore separate design concerns. A synchronous counter makes multi-bit state evaluation more predictable by using a common clock.

Unit 12: Registers and Shift Registers

A register stores a multi-bit word in a set of flip-flops. A load-enable register changes state only when its control is asserted.

Shift registers move data one position per clock. They can support:

• serial-in/serial-out,
• serial-in/parallel-out,
• parallel-in/serial-out,
• parallel-in/parallel-out,
• bidirectional shifting.

They are used in serialization, delay lines, simple sequence generators and data conversion between serial and parallel interfaces.

A universal shift register usually combines hold, left shift, right shift and parallel load under mode controls.

Unit 13: Memory and Programmable Logic

13.1. ROM and RAM Concepts

ROM-like devices store a mapping from address to data. RAM supports read and write operations. In digital-design terms, a ROM can also implement combinational logic: input variables form an address and stored bits form function outputs.

SRAM stores state in bistable cells and does not need refresh while powered. DRAM stores charge in capacitive cells and requires periodic refresh. Their density, latency and implementation characteristics differ substantially.

13.2. Programmable Logic

PROM, PLA and PAL structures historically illustrated the idea of programmable product/sum planes. Modern CPLDs and FPGAs generalize programmable logic with configurable logic elements, routing and embedded resources.

An FPGA implementation should be described synchronously and with explicit clock-domain, reset and timing assumptions. HDL syntax is not a software execution sequence; it specifies hardware structure and behavior that synthesis maps to circuitry.

13.3. Memory Terminology: Words, Addresses, and Buses

A memory is often modeled as an array of addressable words.

For example:

4096 x 16

means:

4096 addressable words
16 bits per word
65536 total bits
12 address bits
16 data bits

Its external interface can be understood through address lines, data lines, and control signals.

13.4. Volatile and non-volatile Memory

Volatile storage loses state when power is removed. SRAM and DRAM belong to this class.

Non-volatile storage retains information without continuous power. ROM derivatives, EEPROM, and flash are examples.

Logical function and physical cell technology should remain separate concepts.

13.5. SRAM and DRAM

SRAM uses bistable storage and does not require refresh while powered. DRAM stores charge and requires periodic refresh.

A broad trade-off is:

SRAM:
low latency
larger cell area

DRAM:
high density
refresh requirement

This distinction connects register files and caches to main-memory organization.

13.6. ROM, PROM, EPROM, EEPROM, and Flash

Historically important non-volatile categories include:

mask ROM   -> defined during manufacture
PROM       -> one-time user programming
EPROM      -> ultraviolet-erasable historical technology
EEPROM     -> electrically erasable/writable
flash      -> block-oriented erase/write non-volatile memory

Their exact programming mechanisms and endurance are technology-specific.

13.7. Expanding Memory

Capacity can grow in two different dimensions.

Increase the number of words:

2 x (1K x 8)
-> selection logic
2K x 8

Increase word width:

2 x (1K x 8)
-> parallel data paths
1K x 16

These operations require different address and data interconnections.

13.8. Programmable Logic Arrays

PROM, PLA, PAL, and GAL provide historically useful models for mapping Boolean expressions into programmable AND/OR structures.

A conceptual summary is:

PROM:
fixed AND / programmable OR

PLA:
programmable AND / programmable OR

PAL:
programmable AND / more constrained OR

GAL:
reprogrammable PAL-like historical family

Commercial implementations vary, but the abstraction illustrates how SOP/POS logic can be mapped into programmable hardware.

13.9. From CPLDs to FPGAs

Modern programmable logic contains far richer resources than classic fuse arrays.

An FPGA commonly provides:

LUTs
flip-flops
carry chains
routing
block RAM
clock resources
DSP blocks
I/O resources

A LUT implements a Boolean function by storing a small truth table. Six-input LUTs are common in selected FPGA families, although exact structure is architecture-specific.

Synthesis maps HDL behavior into these resources:

Boolean expression
-> RTL
-> synthesis
-> LUT / carry / register / memory resources

13.10. Reset Choices Affect Implementation Resources

Adding reset to every register is not automatically safer.

Reset networks can create high fanout, complicate routing, prevent efficient inference of shift-register or memory resources, and affect frequency, area, and power.

Reset requirements should therefore be determined by function rather than applied mechanically to every datapath register.

13.11. Separating Latency from Throughput

In digital logic, the longest combinational path constrains the clock period. Register insertion can shorten that path and increase clock frequency, while also increasing the number of cycles required for one datum to reach the output. Propagation delay, setup and hold requirements, clock skew, and pipeline occupancy must be examined separately. A higher synthesized clock frequency in an FPGA or ASIC does not automatically imply lower end-to-end latency.

• Separate the effect of pipeline depth on single-operation latency from aggregate throughput.
• Account for register and control overhead when shortening the critical path.
• Verify digital blocks against timing budgets as well as functional behavior.

Unit 14: State Machines

14.1. State-table Model

A finite-state sequential circuit can be represented by:

next_state = f(current_state, input)
output     = g(current_state, input)

for a Mealy model, or:

output = g(current_state)

for Moore-style output.

Design steps are typically:

1. identify states,
2. define transitions,
3. form a state diagram/table,
4. choose state encoding,
5. derive next-state/output logic,
6. verify reachable and exceptional states.

State assignment affects logic complexity, switching and implementation. Binary, one-hot and Gray-like encodings have different tradeoffs.

14.2. Expanded State Tables

An expanded table can include current state, input, next state, outputs and the flip-flop excitation values required by the chosen storage element. For D flip-flops, next-state bits directly become D inputs. For JK or T flip-flops, excitation equations must be derived.

14.3. State-machine Synthesis and Unreachable States

A synchronous finite-state machine separates state storage from next-state and output logic. Moore outputs depend only on state; Mealy outputs can also depend directly on current inputs.

A robust design flow is:

requirements
-> state definition
-> transition table
-> state encoding
-> next-state/output equations
-> timing verification

Unused state encodings should not be ignored automatically. In safety-relevant logic, the design may define a recovery transition from every illegal state to a known safe state.

Counter design follows the same principle. Ripple counters propagate timing through stages, while synchronous counters compute the next state under a common clock and are easier to reason about at higher clock rates.

Unit 15: Electrical Reality of Logic and Logic Families

Boolean 0 and 1 are abstract values. Physical circuits represent them with voltage and current ranges, so real digital design must satisfy both logical correctness and electrical compatibility.

15.1. Input and Output Thresholds

Logic data sheets commonly define:

VIL(max) -> highest input guaranteed as logic 0
VIH(min) -> lowest input guaranteed as logic 1

VOL(max) -> highest guaranteed low output
VOH(min) -> lowest guaranteed high output

The region between VIL(max) and VIH(min) is not a guaranteed logic state.

15.2. Noise Margins

Simplified noise margins are:

NMH = VOH(min) - VIH(min)
NML = VIL(max) - VOL(max)

Positive margin represents tolerance between the level guaranteed by a driver and the threshold required by a receiver.

15.3. Fan-out Is More Than a Gate Count

In historical TTL discussions, fan-out is often calculated from input and output currents.

Modern CMOS inputs can have very small static current while still presenting capacitance. At higher speed, practical drive capability therefore depends on DC current, capacitive load, edge rate, and target frequency.

15.4. Source and Sink Current

A high output can source current toward a load; a low output can sink current toward ground.

Guaranteed source and sink capability may differ. Loads such as LEDs and wide fanout networks require both voltage and current specifications to be checked.

15.5. Propagation Delay

A physical gate does not respond instantaneously.

Typical parameters include:

tPLH -> low-to-high propagation delay
tPHL -> high-to-low propagation delay

Delay accumulates across logic depth.

15.6. Power and Switching

CMOS can have low static power, but switching charges and discharges capacitance.

A simplified dynamic-power relationship is:

P_dynamic ∝ C × V² × f

so larger capacitance, higher voltage, and higher switching frequency increase dynamic power.

15.7. TTL, CMOS, and ECL in Historical Context

TTL, CMOS, and ECL represent different speed, power, voltage, and implementation trade-offs in digital-electronics history.

ECL targeted very high speed through non-saturating bipolar structures. TTL became a major 5-V logic family. CMOS became dominant in modern integrated digital systems because of density, low static power, and voltage scaling.

CMOS is not one universal electrical standard. HC, HCT, AHC, LVC, and other families differ in thresholds, supply ranges, speed, and drive strength. Real component selection must follow the device data sheet.

15.8. Open-collector and open-drain Outputs

Open-collector or open-drain outputs actively drive only one direction; the opposite level is established by an external pull-up.

This can support shared lines, wired logic, and selected level-translation arrangements.

Ordinary push-pull CMOS outputs must not be treated the same way; directly tying conflicting drivers together can create excessive current.

15.9. Three-state Outputs

A three-state driver has:

0
1
Z

where Z is high impedance rather than a third logic value.

In modern FPGA internal fabric, HDL tri-state descriptions are commonly synthesized into multiplexers; physical three-state behavior is normally available at I/O boundaries.

15.10. Floating and Slow CMOS Inputs

CMOS inputs should not be left floating. Inputs held in the threshold region or changing too slowly can cause unnecessary current and unstable behavior.

Unused inputs should be tied to a defined level according to the device data sheet.

15.11. Schmitt-trigger Inputs

A Schmitt-trigger input uses hysteresis with different rising and falling thresholds.

It can convert a slow or noisy external signal into a cleaner digital transition.

A Schmitt trigger is not a replacement for clock-domain synchronization; electrical signal conditioning and metastability control are different problems.

15.12. Level Translation

Before connecting devices with different supply voltages, check VOH/VOL, VIH/VIL, absolute-maximum ratings, input tolerance, and output-current limits.

General voltage rules are not substitutes for device specifications. A dedicated level translator may be required.

15.13. Connecting RTL Results to Hardware Reality

A design that passes functional simulation can still fail in hardware because of timing, metastability, or reset-release behavior. Truth tables and RTL simulation are therefore only the first verification layer.

Clock-domain crossings require different techniques for single-bit controls, multi-bit data, and counters. CDC analysis, timing constraints, and post-synthesis reports make the design assumptions explicit. Metastability cannot be eliminated completely; its probability is managed.

FPGA/ASIC examples should identify the target family, clock rate, and relevant primitives. This separates general digital-logic principles from vendor-specific resource behavior.

Unit 16: Multivibrators, Pulse Conditioning, and Asynchronous Inputs

A multivibrator is a historically important classification of feedback switching circuits by the number of stable states.

16.1. Bistable

A bistable circuit has two stable states. Latches and flip-flops are the core digital examples.

16.2. Monostable

A monostable circuit has one stable state and one temporary state.

A trigger causes a temporary output pulse, after which the circuit returns automatically to its stable state.

Applications include one-shot pulse generation, minimum pulse width, and edge-to-pulse conversion.

Timing may be created with analog RC elements, a timer device, or a digital counter depending on the design.

16.3. Astable

An astable circuit has no stable state and oscillates continuously.

Simple RC oscillators are useful teaching examples, but a high-integrity synchronous system clock should normally come from a timing source with defined characteristics such as a crystal oscillator, PLL/MMCM, or dedicated clock generator.

16.4. Switch Bounce

A mechanical switch can create many short transitions during one physical press:

ideal:
____|‾‾‾‾

real:
____|_|‾|_|‾‾‾

Driving a counter clock directly from this waveform can count one press several times.

Debouncing can use a Schmitt-trigger/RC network, an SR latch, synchronous sampling, or a minimum-stability-time rule.

16.5. Bringing an Asynchronous Input into a Clock Domain

A button, sensor, interrupt, or another clock domain can be asynchronous to the local clock.

A common single-bit synchronizer is:

async input
   ↓
FF1
   ↓
FF2
   ↓
synchronous domain

The first flip-flop can become metastable; the second stage provides resolution time. The structure reduces failure probability rather than mathematically eliminating metastability.

Synchronizing each bit of a multi-bit bus independently does not guarantee a coherent word. Handshakes, Gray-coded counters, asynchronous FIFOs, or other protocols are required.

16.6. Clock Enable versus ad-hoc Clock Gating

Combining a clock and logic condition through an ordinary gate can create short or malformed clock pulses.

Modern FPGA and ASIC design should use dedicated clock-enable structures, approved clock-gating cells, and supported clock resources.

Generating a pulse and distributing a reliable clock are different engineering problems.

16.7. Clock-domain Crossing, Metastability, and Reset Design

Synchronous design becomes unsafe when signals are assumed to share a clock domain without proof. A control bit arriving asynchronously can drive a receiving flip-flop into metastability. Two-stage synchronizers are common for single-bit controls; multi-bit transfers need protocols such as handshakes, Gray-coded counters, or asynchronous FIFOs.

Reset behavior is also a clock-domain problem. Designers must define how reset is asserted and released, especially across unrelated clocks.

CDC and reset-domain analysis complement functional simulation because intermittent hardware failures may never appear in ordinary RTL simulation.

16.8. Hazards, Synthesis, and Static Timing

A truth table describes the logical result that a circuit should produce, but physical gates and interconnects do not have zero delay. Two implementations of the same Boolean function can therefore behave differently during transitions.

16.9. Hazards

When an input changes, unequal propagation delay through different logic paths can create a transient incorrect pulse. This is a hazard.

logically:        1 -------- 1
physical change:  1 ---0---- 1

A static hazard temporarily changes a value that should have remained constant. A dynamic hazard produces multiple transitions where only one was expected. A synchronous design may tolerate some internal glitches, but the result can become critical when an asynchronous control path or another clock domain samples them.

16.10. RTL Is Not the Synthesized Circuit

RTL describes intended clocked behavior. Synthesis maps that behavior to gates, multiplexers, registers, and target-technology cells. The same RTL may produce different netlists under different optimization targets or FPGA/ASIC technologies.

Therefore:

RTL simulation
!=
synthesized logic
!=
post-place-and-route timing

Functional simulation answers a logical question; physical timing analysis answers a separate timing question.

16.11. Static Timing Analysis

A simplified synchronous timing constraint can be read as:

Tclk >= Tcq + Tcomb + Tsetup + Tskew

The source register's clock-to-Q delay, combinational-path delay, destination setup requirement, and clock-distribution difference all participate in the timing budget.

The hold condition is different: new data must not reach the destination before the previous value has been sampled safely. Lowering clock frequency may help a setup violation but does not automatically repair a hold violation.

16.12. Timing Constraints Are Design Inputs

Without clock periods, input/output delays, and explicit exceptions such as false or multicycle paths, synthesis and timing tools do not know the complete timing contract of the design. A design that "synthesizes successfully" is not therefore proven to operate reliably at the target frequency.

Digital verification should answer three distinct questions:

1. Is the logical function correct?
2. Are clock-domain and reset boundaries safe?
3. Do physical path delays satisfy the timing budget?

16.13. Metastability and Event Loss at Asynchronous Inputs

A digital input originating from another clock domain or an external circuit can violate a receiving flip-flop's setup and hold constraints. Its output may then take additional time to settle to a stable logic level. Metastability is not a software bug that can be completely eliminated. A two-flip-flop synchronizer clocked in the destination domain provides additional settling time and reduces the probability of propagation into downstream logic. It does not guarantee that every narrow pulse will be observed.

A pulse narrower than the receiving clock interval can fall entirely between sampling edges. A two-stage synchronizer is appropriate for a persistent one-bit level; a short event may require toggle encoding or request–acknowledge handshaking. Synchronizing the bits of a multi-bit word independently also does not create an atomic transfer: old and new bits can be mixed. Gray-coded counters, asynchronous FIFOs, or handshakes are alternatives only under their respective design assumptions.

Verification must extend beyond ideal-clock functional simulation. Clock-rate ratios, phase offsets, pulse widths, reset behavior, and tolerated event loss or duplication belong in the design contract. Mean-time-between-failure reasoning expresses synchronizer reliability probabilistically; it is not a zero-risk guarantee.

Unit 17: The Analog-Digital Boundary, ADCs, and DACs

Digital logic operates on discrete symbols, while the physical world commonly produces continuous voltage, current, temperature, pressure, and sound.

The boundary is implemented through analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

17.1. Three Conceptual Stages of an ADC

ADC behavior can be separated into:

sampling
↓
quantization
↓
encoding

Sampling measures the analog signal at selected times. Quantization maps a measured value to one of a finite number of levels. Encoding emits the selected level as a bit pattern.

An ideal n-bit ADC can produce up to 2^n codes.

For an ideal full-scale reference Vref, an approximate code step is:

LSB ≈ Vref / 2^n

Real converters also include offset, gain error, nonlinearity, noise, and clock-related effects.

17.2. DAC

A DAC maps a digital word to an analog voltage or current.

digital code
   ↓
weighted conversion
   ↓
analog voltage/current

Resistor ladders, current-steering structures, and capacitor arrays are different physical implementations.

17.3. Successive Approximation

A successive-approximation ADC tries bits from most significant to least significant.

try a bit
↓
internal DAC creates analog candidate
↓
compare with input
↓
keep or clear bit
↓
continue

It is a useful system-level example combining a register, DAC, comparator, and control state machine.

17.4. Boundary with Electronics

Bit coding, control state, and successive-approximation logic belong naturally to digital design.

Sampling circuits, comparator analog performance, references, and transistor/op-amp implementation are better treated in Electronics I and II: Analog and Digital Circuit Fundamentals.

References

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